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SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1788
Advance Information
98 RGB x 68 CSTN www..com LCD Segment / Common COLOR Driver with Controller
This document contains information on a new product. Specifications and information herein are subject to change without notice. http://www.solomon-systech.com SSD1788 Series Rev 1.2 P 1/71 Jul 2004 Copyright 2003 Solomon Systech Limited
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TABLE OF CONTENTS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 GENERAL DESCRIPTION ...................................................................................................................... 5 FEATURES .............................................................................................................................................. 5 ORDERING INFORMATION ................................................................................................................... 5 BLOCK DIAGRAM .................................................................................................................................. 6 DIE PAD FLOOR PLAN .......................................................................................................................... 7 PIN DESCRIPTION................................................................................................................................ 14 FUNCTIONAL BLOCK DESCRIPTIONS .............................................................................................. 17 COMMAND TABLE ............................................................................................................................... 24 COMMAND DESCRIPTIONS ................................................................................................................ 33 MAXIMUM RATINGS ............................................................................................................................ 53 DC CHARACTERISTICS....................................................................................................................... 54 AC CHARACTERISTICS....................................................................................................................... 56 APPLICATION EXAMPLES .................................................................................................................. 67 PACKAGE INFORMATION................................................................................................................... 70
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Solomon Systech
Jul 2004
P 2/71
Rev 1.2
SSD1788 Series
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TABLE OF TABLES
Table 1 - Ordering Information .............................................................................................................................5 Table 2 - SSD1788 Series Bump Die Pad Coordinates .......................................................................................8 Table 3 - VOUT > VL5 > VL4 > VL3 > VL2 > VSS Relationship ..................................................................................15 Table 4 - Data bus selection modes ...................................................................................................................18 Table 5 - Command Table ..................................................................................................................................24 Table 6 - Read Command Table ........................................................................................................................31 Table 7 - RAM arrangements of 8-levels gray scale mode ................................................................................33 Table 8 - RAM arrangements of 16-levels gray scale mode ..............................................................................34 Table 9 - RGB Arrangement modes ...................................................................................................................37 Table 10 - Gray scale selection mode ................................................................................................................37 Table 11 - Area scrolling selection modes..........................................................................................................39 Table 12 - Maximum Ratings..............................................................................................................................53 Table 13 - DC Characteristics ............................................................................................................................54 Table 14 - AC Characteristics.............................................................................................................................56 Table 15 - Parallel 6800-series Interface Timing Characteristics.......................................................................57 Table 16 - Parallel 8080-series Interface Timing Characteristics.......................................................................58 Table 17 - Parallel 6800-series Interface Timing Characteristics.......................................................................59 Table 18 - Parallel 8080-series Interface Timing Characteristics.......................................................................60 Table 19 - 4-Wires Serial Timing Characteristics ...............................................................................................61 Table 20 - 3-Wires Serial Timing Characteristics ...............................................................................................62 Table 21 - 4-Wires Serial Timing Characteristics ...............................................................................................63 Table 22 - 3-Wires Serial Timing Characteristics ...............................................................................................64 Table 23 - Power Up/Down Timing Characteristics............................................................................................65
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SSD1788 Series
Rev 1.2
P 3/71
Jul 2004
Solomon Systech
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TABLE OF FIGURES
Figure 1 - SSD1788 Block Diagram..................................................................................................................................... 6 Figure 2 - SSD1788 Die Pad Floor Plan ............................................................................................................................... 7 Figure 3 - Display Data....................................................................................................................................................... 17 Figure 4 - Display Data RAM Map .................................................................................................................................... 21 Figure 5 - SSD1788 Hardware Configurations................................................................................................................... 22 Figure 6 - Oscillator structural block diagram .................................................................................................................... 22 Figure 7 - column and page scan direction of 8-level gray scale mode .............................................................................. 35 Figure 8 - column and page scan direction of 16-level gray scale mode ............................................................................ 36 Figure 9 - Example of Normal or Reverse page/column/ scan directions........................................................................... 36 Figure 10 - Examples: 8 gray-scale display arrangement ................................................................................................... 37 Figure 11 - Area scrolling selection modes ........................................................................................................................ 39 Figure 12 - GDDRAM updates for area scrolling............................................................................................................... 40 Figure 13 - Example of Specified Center Scroll Mode....................................................................................................... 41 Figure 14 - Contrast Control Flow Set Segment Re-map ................................................................................................... 42 Figure 15 - Contrast Control Voltage Range Curve............................................................................................................ 43 Figure 16 - Partial display mode......................................................................................................................................... 44 Figure 17 - OTP programming circuitry ............................................................................................................................. 49 Figure 18 - Flow chart of OTP programming Procedure.................................................................................................... 50 Figure 19 - Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H) ..................................................... 57 Figure 20 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L)...................................................... 58 Figure 21 - Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H) ..................................................... 59 Figure 22 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L)...................................................... 60 Figure 23 - 4-Wires Serial Timing Characteristics (PS0 = L, PS1 =L) .............................................................................. 61 Figure 24 - 3-Wires Serial Timing Characteristics (PS0 = L, PS1 =H) .............................................................................. 62 Figure 25 - 4-Wires Serial Timing Characteristics (PS0 = L, PS1 =L) .............................................................................. 63 Figure 26 - 3- Wires Serial Timing Characteristics (PS0 = L, PS1 =H) ............................................................................. 64 Figure 27 - Power Up ......................................................................................................................................................... 65 Figure 28 - Initial Code Timing Chart ................................................................................................................................ 66 Figure 29 - Power save / power up / power off timing chart .............................................................................................. 66 Figure 30 - Application Examples ...................................................................................................................................... 67
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Solomon Systech
Jul 2004
P 4/71
Rev 1.2
SSD1788 Series
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1
General Description
SSD1788 is a single-chip CMOS color STN LCD driver with controller for dot-matrix graphic liquid crystal display system. SSD1788 consists of 362 high voltage driving output pins for driving maximum 98 RGB Segments and 68 Commons. SSD1788 consists of 294 (98 RGB) x 68 x 4 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent from common MCU through 8-bit 6800-series / 8080-series compatible Parallel Interface or 3-wires / 4wires Serial Peripheral Interface by pins selection. SSD1788 embeds DC-DC Converter, On-Chip Oscillator and Bias Divider so as to reduce the number of external components. With the advanced design, low power consumption, stable LCD operating voltage and flexible die package layout, SSD1788 is suitable for any portable battery-driven applications requiring long operation period with compact size.
2
FEATURES
* * * * * * * * * * * * * * * * * * * * Power Supply: VDD = 2.4 V - 3.6V VDDIO = 1.2 V - 3.6V VCI = 2.4V - 3.6V LCD Driving Output Voltage: 13.5V Low Current Sleep Mode Maximum display size: 98 RGB columns by 68 rows. Maximum display colors: 256 colors or 4096 colors graphical display 256-colors Position Control and simultaneous RGB display control 8-bit 6800-series / 8080-series Parallel Interface, 3-wires /4-wires Serial Peripheral Interface On-Chip 294 (98 RGB) X 68 x 4 = 79,968 bits Graphic Display Data RAM Programmable partial display function Column Re-mapping and RAM Page scan direction control Software selection on Center Screen Scrolling, Top Screen Scrolling, Bottom Screen Scrolling and Whole Screen Scrolling On-Chip Voltage Generator or External LCD Driving Power Supply Selectable 3X/ 4X / 5X / 6X On-Chip DC-DC Converter with internal flying capacitor 64 Levels Internal Contrast Control Programmable LCD Driving Voltage Temperature Compensation Coefficients On-Chip Bias Divider with internal flying capacitor (expect VOUT) Programmable drive duty ratio: 1 /8 to 1 /68 On-Chip Oscillator 2-D Graphic Acceleration Engine Non-Volatile Memory (OTP) for calibration
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3
ORDERING INFORMATION
Ordering Part Number SSD1788Z SEG 98x3 (294) COM 68 Package Form Gold Bump Die Reference Remark
Figure 2 on
Page 7
Table 1 - Ordering Information
SSD1788 Series
Rev 1.2
P 5/71
Jul 2004
Solomon Systech
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4
BLOCK DIAGRAM
ROW0
~
ROW67
COL0
~ COL293
68 Common Driver Circuits
98 RGB Segment Driver Circuits
VOUT VL4 VL3
VL2 VL5
VSS
Display Data Latch
LCD Driving Voltage Generator 3X/4X/5X/6X DC/DC Converter, Voltage Regulator, Contrast Control, Bias Divider, Temperature Compensation
BUSY SYN Display Timing Generator GDDRAM 294 (98RGB) X 68 X4 bits Page Address Control Circuit Column Address Control Circuit
VCIX2
M
VCI
VLREF VHREF
CL
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Oscillator MPU System Control Circuit
2-D Graphic Acceleration Engine
Status Register
TEST1 Command Decoder TEST18
VDD VDDIO VSS CVSS Microprocessor Interface Logic RVSS
( WR ) ( RD )
R/ W
E
CS
D/C
RES
PS0
PS1 D0
-
D7
Figure 1 - SSD1788 Block Diagram
Solomon Systech
Jul 2004
P 6/71
Rev 1.2
SSD1788 Series
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5
DIE PAD FLOOR PLAN
Note: 1. Diagram showing the die face up. 2. Coordinates are reference to center of the chip. 3. Unit of coordinates and Size of all alignment marks are in um. 4. All alignment keys do not contain gold bump.
KEY1 CENTER:-7513,371.5
PIN 1
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(0,0)
100
KEY3 CENTER:-7563.9,-448 KEY4 CENTER:7563.9,-448
25
25
25
25
25
100
25
100
25
25
25
25
100
y
50
x
Die Size Die Thickness Typical Bump Height Bump Co-planarity (within die)
KEY2 CENTER:7513,371.5
75 18
100
100
15.68 x 1.65 mm 45725 m 15 m <3 m
2
Figure 2 - SSD1788 Die Pad Floor Plan
SSD1788 Series
Rev 1.2
P 7/71
Jul 2004
Solomon Systech
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Table 2 - SSD1788 Series Bump Die Pad Coordinates (Bump center)
Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 X-pos Y-pos Pad # -7714.5 -663 51 -7638.2 -663 52 -7553.7 -663 53 -7477.4 -663 54 -7401.1 -663 55 -7324.8 -663 56 -7248.5 -663 57 -7172.2 -663 58 -7095.9 -663 59 -7019.6 -663 60 -6943.3 -663 61 CS -6867 -663 62 CS VDD -6790.7 -663 63 -6714.4 -663 64 RES -6638.1 -663 65 RES D/C -6561.8 -663 66 D/C -6485.5 -663 67 VSS -6409.2 -663 68 -663 69 R / W ( WR ) -6332.9 -663 70 R / W ( WR ) -6256.6 E ( RD ) -6180.3 -663 71 E ( RD ) -6104 -663 72 VDD -6027.7 -663 73 D7 (SDA) -5951.4 -663 74 D7 (SDA) -5875.1 -663 75 D0 -5798.8 -663 76 D1 -5722.5 -663 77 D2 -5646.2 -663 78 D3 -5569.9 -663 79 D4 -5493.6 -663 80 D5 -5417.3 -663 81 D6 ( SCK) -5341 -663 82 D6 ( SCK) -5264.7 -663 83 D6 ( SCK) -5188.4 -663 84 D7 (SDA) -5112.1 -663 85 D7 (SDA) -5035.8 -663 86 D7 (SDA) -4959.5 -663 87 D0 -4883.2 -663 88 VDD -4806.9 -663 89 -4730.6 -663 90 CS -4654.3 -663 91 CS VSS -4578 -663 92 -4501.7 -663 93 RES -4425.4 -663 94 RES -4349.1 -663 95 D/C -4272.8 -663 96 D/C BUSY -4196.5 -663 97 BUSY -4120.2 -663 98 VDDIO -4043.9 -663 99 VDDIO -3967.6 -663 100 Signal DUMMY DUMMY CL M SYN VDD PS0 VSS PS1 VSS Signal TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VLREF VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI X-pos Y-pos Pad # -3891.3 -663 101 -3815 -663 102 -3738.7 -663 103 -3662.4 -663 104 -3586.1 -663 105 -3509.8 -663 106 -3433.5 -663 107 -3357.2 -663 108 -3280.9 -663 109 -3204.6 -663 110 -3128.3 -663 111 -3052 -663 112 -2975.7 -663 113 -2899.4 -663 114 -2823.1 -663 115 -2746.8 -663 116 -2670.5 -663 117 -2594.2 -663 118 -2517.9 -663 119 -2441.6 -663 120 -2365.3 -663 121 -2289 -663 122 -2212.7 -663 123 -2136.4 -663 124 -2060.1 -663 125 -1983.8 -663 126 -1907.5 -663 127 -1831.2 -663 128 -1754.9 -663 129 -1678.6 -663 130 -1602.3 -663 131 -1526 -663 132 -1449.7 -663 133 -1373.4 -663 134 -1297.1 -663 135 -1220.8 -663 136 -1144.5 -663 137 -1068.2 -663 138 -991.9 -663 139 -915.6 -663 140 -839.3 -663 141 -763 -663 142 -686.7 -663 143 -610.4 -663 144 -534.1 -663 145 -457.8 -663 146 -381.5 -663 147 -305.2 -663 148 -228.9 -663 149 -152.6 -663 150 Signal VCI VCI VCI VCI VCI VCI VHREF RVSS RVSS RVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS CVSS TEST10 TEST11 TEST12 TEST13 TEST14 TEST15 TEST16 TEST17 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS X-pos Y-pos -76.3 -663 0 -663 76.3 -663 152.6 -663 228.9 -663 305.2 -663 381.5 -663 457.8 -663 534.1 -663 610.4 -663 686.7 -663 763 -663 839.3 -663 915.6 -663 991.9 -663 1068.2 -663 1144.5 -663 1220.8 -663 1297.1 -663 1373.4 -663 1449.7 -663 1526 -663 1602.3 -663 1678.6 -663 1754.9 -663 1831.2 -663 1907.5 -663 1983.8 -663 2060.1 -663 2136.4 -663 2212.7 -663 2289 -663 2365.3 -663 2441.6 -663 2517.9 -663 2594.2 -663 2670.5 -663 2746.8 -663 2823.1 -663 2899.4 -663 2975.7 -663 3052 -663 3128.3 -663 3204.6 -663 3280.9 -663 3357.2 -663 3433.5 -663 3509.8 -663 3586.1 -663 3662.4 -663
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Solomon Systech
Jul 2004
P 8/71
Rev 1.2
SSD1788 Series
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Pad #
Signal X-pos 3738.7 3815 3891.3 3967.6 4043.9 4120.2 4196.5 4272.8 4349.1 4425.4 4501.7 4578 4654.3 4730.6 4806.9 4883.2 4959.5 5035.8 5112.1 5188.4 5264.7 5341 5417.3 5493.6 5569.9 5646.2 5722.5 5798.8 5875.1 5951.4 6027.7 6104 6180.3 6256.6 6332.9 6409.2 6485.5 6561.8 6638.1 6714.4 6790.7 6867 6943.3 7019.6 7095.9 7172.2 7248.5 7324.8 7401.1 7477.4
Y-pos -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663 -663
Pad # 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238
Signal CL DUMMY DUMMY DUMMY ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 ROW9 ROW10 ROW11 ROW12 ROW13 ROW14 ROW15 ROW16 ROW17 ROW18 ROW19 ROW20 ROW21 ROW22 ROW23 ROW24 ROW25 ROW26 ROW27 ROW28 ROW29 ROW30 ROW31 ROW32 ROW33
X-pos 7553.7 7638.2 7714.5 7718.5 7665 7623 7581 7539 7497 7455 7413 7371 7329 7287 7245 7203 7161 7119 7077 7035 6993 6951 6909 6867 6825 6783 6741 6699 6657 6615 6573 6531 6489 6447 6405 6363 6321 6279
Y-pos -663 -663 -663 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651
Pad # 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276
151 VSS 152 VSS 153 VSS 154 VSS 155 VSS 156 VSS 157 VSS 158 VSS 159 VSS 160 VSS 161 VLREF 162 VL2 163 VL2 164 VL3 165 VL3 166 VLREF 167 VCIX2 168 VCIX2 169 VCIX2 170 VCIX2 171 VCIX2 172 VCIX2 173 VCIX2 174 VCIX2 175 VCIX2 176 VL4 177 VL4 178 VL5 179 VL5 180 TEST18 181 VCIX2 182 VCIX2 183 VCI 184 VHREF 185 VOUT 186 VOUT 187 VOUT 188 VOUT 189 190 191 192 193 194 195 196 197 198 199 200 VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT SYN CL M
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SEG89 SEG88 SEG87
Pad Name COL293 COL292 COL291 COL290 COL289 COL288 COL287 COL286 COL285 COL284 COL283 COL282 COL281 COL280 COL279 COL278 COL277 COL276 COL275 COL274 COL273 COL272 COL271 COL270 COL269 COL268 COL267 COL266 COL265 COL264 COL263 COL262 COL261 COL260 COL259 COL258 COL257 COL256
Signal SEG97
Color B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R
X-pos 6153 6111 6069 6027 5985 5943 5901 5859 5817 5775 5733 5691 5649 5607 5565 5523 5481 5439 5397 5355 5313 5271 5229 5187 5145 5103 5061 5019 4977 4935 4893 4851 4809 4767 4725 4683 4641 4599 4557 4515 4473 4431 4389 4347 4305 4263 4221 4179
Y-pos 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651
SEG96
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG86
SEG85
277 278 279 280 281 282 283 284 285 286
COL255 COL254 COL253 SEG84 COL252 COL251 COL250 SEG83 COL249 COL248 COL247 SEG82 COL246
SSD1788 Series
Rev 1.2
P 9/71
Jul 2004
Solomon Systech
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Pad # 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334
Pad Name COL245 COL244 COL243 COL242 COL241 COL240 COL239 COL238 COL237 COL236 COL235 COL234 COL233 COL232 COL231 COL230 COL229 COL228 COL227 COL226 COL225 COL224 COL223 COL222 COL221 COL220 COL219 COL218 COL217 COL216 COL215 COL214 COL213 COL212 COL211 COL210 COL209 COL208 COL207 COL206 COL205 COL204 COL203 COL202 COL201 COL200 COL199 COL198
Signal SEG81
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
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SEG73 SEG57 SEG72 SEG56 SEG71 SEG55
SEG70
SEG69
SEG68
SEG67
SEG66
Color B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R
X-pos Y-pos Pad # 4137 651 335 4095 651 336 4053 651 337 4011 651 338 3969 651 339 3927 651 340 3885 651 341 3843 651 342 3801 651 343 3759 651 344 3717 651 345 3675 651 346 3633 651 347 3591 651 348 3549 651 349 3507 651 350 3465 651 351 3423 651 352 3381 651 353 3339 651 354 3297 651 355 3255 651 356 3213 651 357 3171 651 358 3129 651 359 3087 651 360 3045 651 361 3003 651 362 2961 651 363 2919 651 364 2877 651 365 2835 651 366 2793 651 367 2751 651 368 2709 651 369 2667 651 370 2625 651 371 2583 651 372 2541 651 373 2499 651 374 2457 651 375 2415 651 376 2373 651 377 2331 651 378 2289 651 379 2247 651 380 2205 651 381 2163 651 382
Pad Name COL197 COL196 COL195 COL194 COL193 COL192 COL191 COL190 COL189 COL188 COL187 COL186 COL185 COL184 COL183 COL182 COL181 COL180 COL179 COL178 COL177 COL176 COL175 COL174 COL173 COL172 COL171 COL170 COL169 COL168 COL167 COL166 COL165 COL164 COL163 COL162 COL161 COL160 COL159 COL158 COL157 COL156 COL155 COL154 COL153 COL152 COL151 COL150
Signal SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG54
SEG53
SEG52
SEG51
SEG50
Color B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R
X-pos Y-pos 2121 651 2079 651 2037 651 1995 651 1953 651 1911 651 1869 651 1827 651 1785 651 1743 651 1701 651 1659 651 1617 651 1575 651 1533 651 1491 651 1449 651 1407 651 1365 651 1323 651 1281 651 1239 651 1197 651 1155 651 1113 651 1071 651 1029 651 987 651 945 651 903 651 861 651 819 651 777 651 735 651 693 651 651 651 609 651 567 651 525 651 483 651 441 651 399 651 357 651 315 651 273 651 231 651 189 651 147 651
Solomon Systech
Jul 2004
P 10/71
Rev 1.2
SSD1788 Series
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Pad # 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430
Pad Name COL149 COL148 COL147 COL146 COL145 COL144 COL143 COL142 COL141 COL140 COL139 COL138 COL137 COL136 COL135 COL134 COL133 COL132 COL131 COL130 COL129 COL128 COL127 COL126 COL125 COL124 COL123 COL122 COL121 COL120 COL119 COL118 COL117 COL116 COL115 COL114 COL113 COL112 COL111 COL110 COL109 COL108 COL107 COL106 COL105 COL104 COL103 COL102
Signal SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
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SEG41 SEG25 SEG40 SEG24 SEG39 SEG23
SEG38
SEG37
SEG36
SEG35
SEG34
Color B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R
X-pos Y-pos Pad # 105 651 431 63 651 432 21 651 433 -21 651 434 -63 651 435 -105 651 436 -147 651 437 -189 651 438 -231 651 439 -273 651 440 -315 651 441 -357 651 442 -399 651 443 -441 651 444 -483 651 445 -525 651 446 -567 651 447 -609 651 448 -651 651 449 -693 651 450 -735 651 451 -777 651 452 -819 651 453 -861 651 454 -903 651 455 -945 651 456 -987 651 457 -1029 651 458 -1071 651 459 -1113 651 460 -1155 651 461 -1197 651 462 -1239 651 463 -1281 651 464 -1323 651 465 -1365 651 466 -1407 651 467 -1449 651 468 -1491 651 469 -1533 651 470 -1575 651 471 -1617 651 472 -1659 651 473 -1701 651 474 -1743 651 475 -1785 651 476 -1827 651 477 -1869 651 478
Pad Name COL101 COL100 COL99 COL98 COL97 COL96 COL95 COL94 COL93 COL92 COL91 COL90 COL89 COL88 COL87 COL86 COL85 COL84 COL83 COL82 COL81 COL80 COL79 COL78 COL77 COL76 COL75 COL74 COL73 COL72 COL71 COL70 COL69 COL68 COL67 COL66 COL65 COL64 COL63 COL62 COL61 COL60 COL59 COL58 COL57 COL56 COL55 COL54
Signal SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG22
SEG21
SEG20
SEG19
SEG18
Color B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R
X-pos Y-pos -1911 651 -1953 651 -1995 651 -2037 651 -2079 651 -2121 651 -2163 651 -2205 651 -2247 651 -2289 651 -2331 651 -2373 651 -2415 651 -2457 651 -2499 651 -2541 651 -2583 651 -2625 651 -2667 651 -2709 651 -2751 651 -2793 651 -2835 651 -2877 651 -2919 651 -2961 651 -3003 651 -3045 651 -3087 651 -3129 651 -3171 651 -3213 651 -3255 651 -3297 651 -3339 651 -3381 651 -3423 651 -3465 651 -3507 651 -3549 651 -3591 651 -3633 651 -3675 651 -3717 651 -3759 651 -3801 651 -3843 651 -3885 651
SSD1788 Series
Rev 1.2
P 11/71
Jul 2004
Solomon Systech
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Pad # 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526
Pad Name COL53 COL52 COL51 COL50 COL49 COL48 COL47 COL46 COL45 COL44 COL43 COL42 COL41 COL40 COL39 COL38 COL37 COL36 COL35 COL34 COL33 COL32 COL31 COL30 COL29 COL28 COL27 COL26 COL25 COL24 COL23 COL22 COL21 COL20 COL19 COL18 COL17 COL16 COL15 COL14 COL13 COL12 COL11 COL10 COL9 COL8 COL7 COL6
Signal SEG17
SEG16
Color B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R B G R
X-pos Y-pos -3927 651 -3969 651 -4011 651 -4053 651 -4095 651 -4137 651 -4179 -4221 -4263 -4305 -4347 -4389 -4431 -4473 -4515 -4557 -4599 -4641 -4683 -4725 -4767 -4809 -4851 -4893 -4935 -4977 -5019 -5061 -5103 -5145 -5187 -5229 -5271 -5313 -5355 -5397 -5439 -5481 -5523 -5565 -5607 -5649 -5691 -5733 -5775 -5817 -5859 -5901 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651
Pad # Pad Name 527 COL5 528 COL4 529 COL3 530 COL2 531 COL1 532 COL0
Signal SEG1
SEG0
Color B G R B G R
X-pos Y-pos -5943 651 -5985 651 -6027 651 -6069 651 -6111 651 -6153 651
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
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SEG9 SEG8 SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
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Pad # 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567
Signal ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52 ROW53 ROW54 ROW55 ROW56 ROW57 ROW58 ROW59 ROW60 ROW61 ROW62 ROW63 ROW64 ROW65 ROW66 ROW67 DUMMY
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X
X-pos Y-pos -6279 651 -6321 651 -6363 651 -6405 651 -6447 651 -6489 651 -6531 651 -6573 651 -6615 651 -6657 651 -6699 651 -6741 651 -6783 651 -6825 651 -6867 651 -6909 651 -6951 651 -6993 651 -7035 651 -7077 651 -7119 651 -7161 651 -7203 651 -7245 651 -7287 651 -7329 651 -7371 651 -7413 651 -7455 651 -7497 651 -7539 651 -7581 651 -7623 651 -7665 651 -7718.5 651
Bump Size PAD# Pad 1-203 Pad 204 Pad 205 - 566 Pad 567
X [um] 56 50 27 50
Y [um] 92 118 118 118
Pad pitch [um] (Min) 76.3 53.5 42 53.5
Pad pitch
Y
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6
6.1
PIN DESCRIPTION
CS
This pin is the chip selection input. The chip is enabled for MCU communication only when CS is pulled low.
6.2
RES
This pin is the reset signal input. Initialization of the chip is started once the reset pin is pulled low. The minimum pulse width for reset sequence is 10us.
6.3
D/ C
This pin is Data/Command control pin. When the pin is pulled high, the input at D7-D0 is treated as display data. When the pin is pulled low, the input at D7-D0 will be transferred to the command register.
6.4
R/ W ( WR )
This pin is MCU interface input. When 6800 interface mode is selected, this pin will be used as Read/Write R/W selection input. Read mode will be carried out when this pin is pulled high and write mode when this pin is pulled low. When 8080 interface mode is selected, this pin is the Write ( WR ) control signal input. Data write operation is initiated when this pin is pulled low and the chip is selected.
6.5
E(RD )
This pin is MCU interface input. When 6800 interface mode is selected, this pin will be used as the Enable (E) signal. Read/ write operation is initiated when this pin is pulled high and the chip is selected. When 8080 interface mode is selected, this pin is the Read ( RD ) control signal input. Data read operation is initiated when this pin is pulled low and the chip is selected.
6.6
PS0 - PS1
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These pins are the bus interface mode selection input. Different bus interface can be selected changing the setting of these pins. PS1 PS0 MPU Interface L H 8-bit 8080 parallel interface H H 8-bit 6800 parallel interface H L 3-lines serial peripheral interface (SPI) - 9 bits SPI L L 4-lines serial peripheral interface (SPI) Note1: For serial applications, D0 - D5, R/W ( WR ), E( RD ) are recommended to connect VDD. Note2: Read back operation is only available in parallel mode
6.7
D7-D0
These pins are the 8-bit bi-directional data bus in parallel interface mode. D7 is the MSB while D0 is the LSB. When serial mode selected, D7 is the serial data input SDA and D6 is the serial clock input SCK.
6.8
VLREF
This pin is the ground of operation amplifier VL4 and VL5. It must connect to VSS.
6.9
VHREF
This pin is the power supply pin of the operation amplifier VL3.It must connect to VOUT
6.10 VCIX2
This pin is internal reference pin. It must connect to VCI
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6.11 VDD
This pin is the system power supply pin of the logic block.
6.12 VDDIO
This pin is the system power supply pin of I/O buffer. Please refer to Figure on page 69 for connection example.
6.13 VCI
This pin is the reference voltage input for internal DC-DC converter. The DC-DC converter output is equals to the multiple factor (3X, 4X, 5X or 6X) times of VCI with respect to VSS. The maximum output voltage will limit by the max. VOUT characteristic. Note: Voltage at this input pin must be larger than or equal to VDD. (VCI VDD)
6.14 VSS
This pin is the ground of logic.
6.15 RVSS
This pin is the ground of Vref.
6.16 CVSS
This pin is the ground of analog.
6.17 VOUT
This is the most positive voltage supply pin of the chip. It can be supplied externally or generated by the internal DC-DC converter. If the internal DC-DC converter generates the voltage level at VOUT, the voltage level is used for internal referencing only. The voltage level at VOUT pin is not used for driving external circuitry.
6.18 VL5, VL4, VL3 and VL2
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1 : a bias
LCD driving voltages. They can be supplied externally or generated by the internal bias divider. They have the following relationship: VOUT > VL5 > VL4 > VL3 > VL2 > VSS
VL5 VL4 VL3 VL2
(a-1)/a * Vout
(a-2)/a * Vout 2/a * Vout 1/a * Vout
Table 3 - VOUT > VL5 > VL4 > VL3 > VL2 > VSS Relationship
6.19 ROW0 - ROW67
These pins provide the driving signals, COMMON, to the LCD panel.
6.20 COL0 - COL293
These pins provide the LCD driving signals, SEGMENT, to the LCD panel. The Red, Green, Blue colors signal are sent out from the SEGMENT output at the same time. The output voltage level of these pins is VDD during sleep mode or standby mode.
6.21 CL
This pin is the system clock I/O. This pin is the external clock input for the device, which is enabled by using extended command. It should be left open under normal operation. The internal oscillator will be used after power on reset.
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6.22 M
This pin is used for cascade purpose only. It should be left open under normal operation.
6.23 SYN
This pin is used for cascade purpose only. It should be left open under normal operation.
6.24 BUSY
This pin will be high during RAM buffer read/write operation and during graphic commands executing. System programmer should read this pin (low is ready, high is busy) before sending next RAM buffer related command (e.g. RAM write - 5CH; RAM read - 5DH OR any graphic commands)
6.25 TEST1 ~ TEST18
These pins are used for internal only and should be left open, any connection is not allowed.
6.26 Dummy
This is a floating dummy pad without any internal circuitry connection.
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7
7.1
FUNCTIONAL BLOCK DESCRIPTIONS
Microprocessor Interface Logic
The Microprocessor Interface unit consists of three functional blocks for driving the 6800-series parallel interface, 8080-series parallel interface, 3-lines serial peripheral interface and 4-lines serial peripheral interface. The selection of different interface is done by PS0 to PS1 pins. Please refer to the pin descriptions on page 14. a) MPU Parallel 6800-series Interface The parallel Interface consists of 8 bi-directional data pins (D7 - D0), R/W , D/ C , E, CS . R/W ( WR ) input high indicates a read operation from the Graphical Display Data RAM (GDDRAM) or the status register. R/ W input low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of D/ C input. The E input serves as data latch signal (clock) when high provided that CS is low. Please refer to Figure 19 & Figure 20 on page 57 to 58 for Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of the GDDRAM with that of the MCU, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in the following diagram.
R/W ( WR )
E( RD )
DATA BUS
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N write column address dummy read n data read1 n+1 data read 2 n+2 data read 3
Figure 3 - Display Data b) MPU Parallel 8080-series Interface The parallel interface consists of 8 bi-directional data pins D7 - D0, RD , WR , D/ C , CS . RD input serves as data read latch signal (clock) when low provided that CS is low. Whether reading the display data from GDDRAM or reading the status from the status register is controlled by D/ C . WR input serves as data write latch signal (clock) when low provided that CS is low. Whether writing the display data to the GDDRAM or writing the command to the command register is controlled by D/ C . A dummy read is also required before the first actual display data read for 8080-series interface. c) MPU 4-lines Serial Peripheral Interface The 4-lines serial peripheral Interface consists of serial clock SCK, serial data SDA, D/ C , CS . SDA is shifted into 8-bit shift register on every rising edge of SCK in the order of data bit 7, data bit 6 ...... data bit 0. D/ C is sampled on every eighth clock to determine whether the data byte in the shift register is written to the Display Data RAM or command register at the same clock. Please refer to Figure 23 on page 61 for serial interface timing.
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d) MPU 3-lines Serial Peripheral Interface The operation is similar to 4-lines serial peripheral interface while D/ C is not used. There are altogether 9-bits will be shifted into the shift register on every ninth clock in sequence: D/ C bit, D7 to D0 bit. The D/ C bit (first bit of the sequential data) will determine the following data byte in the shift register is written to the Display Data RAM (D/ C bit = 1) or the command register (D/ C bit = 0).
6800 - series Parallel Interface 8-bits 8-bits Status only Yes 8080 - series Parallel Interface 8-bits 8-bits Status only Yes 3-lines or 4-lines Serial peripheral Interface No 8-bits No Yes
Data Read Data Write Command Read Command Write
Table 4 - Data bus selection modes
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Jul 2004
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7.2
Reset Circuit
This block is integrated into the Microprocessor Interface Logic which includes Power On Reset circuitry and the hardware reset pin, RES . Both of these having the same reset function. Once the RES pin receives a negative reset pulse, all internal circuitry will start to initialize. The minimum pulse width for completing the reset sequence is 10us. The status of the chip after reset is given by: When RES input is low, the chip is initialized to the following: 1. Display ON/OFF: Display is OFF 2. Normal/Inverse Display: Normal Display 3. COM Scan Direction: COM0 -> COM67 4. Internal Oscillator: Disable 5. Reference Voltage Generation Circuit: Disable 6. Voltage regulator and Voltage Follower: Disable 7. Booster level: 6X 8. Bias ratio: 1/7(68 Mux) 9. Multiplex ratio: 68 Mux 10. Contrast Level: 32 11. Internal regulator gain: 2.84 o 12. Average temperature gradient: -0.2%/ C 13. Partial display mode: Disable Start COM address: 0 End COM address: 0 14. Area Scroll set Top block address: 0 Bottom block address: 0 Number of specified block: 0 Area scroll mode: Whole screen scroll mode 15. Scroll start set Start block address: 0 16. Data Scan Direction Normal/inverse display of page address: Normal Normal/inverse display of column address: Normal Address-scan direction: Column direction RGB arrangement: RGB Gray-scale setup: 8 gray-scale 17. Start Page Address set: 0 18. End Page Address set: 0 19. Start Column address set: 0 20. End Column address set: 0 21. Select PWM/FRC 2-bit PWM + 2 bit FRC mode
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7.3
Command Decoder
This module determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the D/ C pin. If D/ C pin is high, data is written to Graphic Display data RAM (GDDRAM). If it is low, the input at D7 - D0 is interpreted as a Command and it will be decoded. The decoded command will be written to the corresponding command register.
7.4
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 294 (98 RGB) x 68 x 4 = 79,968 bits. Figure 4 on page 21 is a description of the GDDRAM address map. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software. Please refer to the command "Data Output/Scan direction" in Table 5 on page 24 for detail description. Four pages of display data form a RAM address block and stored in the GDDRAM. Each block will form the fundamental units of scrolling addresses. Various types of area scrolling can be performed by software program according to the command "Set area Scroll" and "Set Scroll Start" in Table 11 on page 39. In order to ease the access of the red, green and blue color data; the 8-bits color data (Red: 3 bits, Green: 3 bits, Blue: 2 bits) is converted to 4-bits data (P10, P11, P12, P13). The 4-bits data are stored into the GDDRAM such that the data are located in the appropriate RAM locations according to the gray scale settings. Please refer to the description section of the command "Set Data Output/Scan Direction" on page 24.
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each cell contains 4-bits data BLOCK PAGE 0 1 2 0 3 4 5 6 1 7 8 9 10 2 11 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 52 53 54 13 55 56 57 58 14 59 60 61 62 15 63 64 65 66 67 16 DATA
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COMMON OUTPUT COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 : : : : : : : : : : : : : : : COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67
SEGMENT
COL285 COL286 SEG95 COL287 COL288 COL289 SEG96 COL290 COL291 COL292 SEG97 COL293
SEG0
SEG1
SEG2
COLUMN
Notes: Page and SEGMENT data scan direction depend on Data Output Scan Direction Setting. Data Output Scan Directin setting cannot affect the Block scan direction.
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COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8
Mapping depends on COM Output scan direction setting
Figure 4 - Display Data RAM Map
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7.5
LCD Driving Voltage Generator and Regulator
This module generates the LCD voltage needed for display output. It takes a single supply input and generates necessary bias voltages. It consists of: 1. 2. 3X, 4X, 5X and 6X DC-DC voltage converter Bias Divider - If the output op-amp buffer option in Set Power Control Register command is enabled, this circuit block will divide the regulator output (VOUT) to give the LCD driving levels (VL2 - VL5). The divider does not require external capacitors to reduce the external hardware and pin counts, power configuration of op-amp is shown on Figure 5 on page 22. Contrast Control -Software control of 64 voltage levels of LCD voltage. Bias Ratio Selection circuitry - Software control of 1/4 to 1/8 bias ratio to match the characteristic of LCD panel. Self adjust temperature compensation circuitry - Provide 4 different compensation grade selections to satisfy the various liquid crystal temperature grades. The grading can be selected by software control. Defaulted temperature coefficient (TC) value is -0.2%/C.
3. 4.
VOUT
+
VHREF
C2
VDD
+ C1
VCI VCIX2 VLREF VSS
SSD1788
Recommended capacitance value: C1: 1uF ~ 2.2uF C2: 2.2uF ~ 4.7uF
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Figure 5 - SSD1788 Hardware Configurations
7.6
Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry (Figure 6). The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in the Display Timing Generator.
Oscillator enable
enable Oscillation Circuit
enable Buffer
(CL)
Internal resistor
OSC1 OSC2
Figure 6 - Oscillator structural block diagram
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7.7
Display Data Latch
This block is a series of latches carrying the display signal information. These latches hold the data, which will be fed to the HV Buffer Cell and Level Selector to output the required voltage level.
7.8
HV Buffer Cell (Level Shifter)
This block is embedded in the Segment/Common Driver Circuits. HV Buffer Cell works as a level shifter, which translates the low voltage output signal to the required driving voltage. The output is shifted out with reference to the internal FRM clock, which comes from the Display Timing Generator. The voltage levels are given by the level selector, which is synchronized with the internal M signal.
7.9
Level Selector
This block is embedded in the Segment/Common Driver circuits. Level Selector is a control of the display synchronization. Display voltage levels can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD waveform.
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8
COMMAND TABLE
Table 5 - Command Table
D/C 0 1 1 Hex 15 D7 D6 D5 D4 0 0 0 1 X7 X6 X5 X4 Y7 Y6 Y5 Y4 D3 0 X3 Y3 D2 1 X2 Y2 D1 0 X1 Y1 D0 1 X0 Y0 Command Set Column Address Description Set the start column address by X7X6X5X4X3X2X1X0 Set the end column address by Y7Y6Y5Y4Y3Y2Y1Y0 Column address = 00000000b (POR) In 8-levels gray scale mode, column address is in a range of 0~97. In 16-level gray scale mode, column address is in a range of 0~48.
0 1 1 0 1
75
0 X7 Y7 1 *
1 X6 Y6 0 *
1 X5 Y5 1 *
1 X4 Y4 1 *
0 X3 Y3 1 *
1 X2 Y2 0 X2
0 X1 Y1 1 X1
1 X0 Y0 1 X0
Set Page Address
Set the start page address by X7X6X5X4X3X2X1X0 Set the end page address by Y7Y6Y5Y4Y3Y2Y1Y0. Page address = 00000000b (POR)
BB
Set COM Output Scan Direction
X2 0 0 0 0
X1 X0 00 01 10 11
ROW0...ROW33 COM0 ->COM33 COM0 ->COM33 COM33<-COM0 COM33<-COM0
ROW34...ROW67 COM34 ->COM67 (POR) COM67 <-COM34 COM34 ->COM67 COM67 <-COM34
0 1 1 1
BC
1 * * *
0 * * *
1 * * *
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1 * * *
1 * * *
1 P12 P22 P32
0 P11 P21 P31
0 P10 P20 P30
Set Data Output Scan Direction
a) Normal or Reverse page/column/scan directions P10 = 0: set page address to normal display (POR) P10 = 1: set page address to inverse display P11 = 0: set column address to normal rotation (POR) P11 = 1: set column address to inverse rotation P12 = 0: set scan direction to column scan (POR) P12 = 1: set scan direction to page scan Please refer to the Figure 7 & Figure 8 on page 35 & 36 respectively for detail description of column/page scan direction modes
b) RGB color arrangement P22, P21, P20: The control bits are used for setting the (RGB) color arrangement of segment output. , 000 is the POR value. Please refer to the Figure 10 on page 37 for detail mapping of the segment output. c) Gray-scale selection P32 P31 P30 Gray-scale modes 0 0 1 8-levels gray scale mode (POR) 0 1 0 16-levels gray scale mode (Type A) Please refer to the Table 9 on page 37 to Table 10on page 37 for detail description of different gray-scale selection modes.
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D/C 0 1 1
Hex CE
1 1
1 1
1 0 1 1 1 CA
D7 D6 D5 D4 1 1 0 0 * * * * * * * * : : * * * * * * * * : : * * * * * * * * : : * * * *
D3 1 X31 X32
D2 1 X21 X22
D1 1 X11 X12
D0 0 X01 X02
Command Set Color Look Up Table (Gray-scale selection: P32 P32 P30 = 001)
X38 X39
X28 X29
X18 X19
X08 X09
Description N DB3 DB2 DB1DB0 color position 1 X3N X2N X1N X0N Intermediate red tone 000 2 X3N X2N X1N X0N Intermediate red tone 001 : : : : 8 X3N X2N X1N X0N Intermediate red tone 111 9 X3N X2N X1N X0N Intermediate green tone 000 : : : :
X316 X317
X216 X217
X116 X117
X016 X017
16 X3N X2N X1N X0N Intermediate green tone 111 17 X3N X2N X1N X0N Intermediate blue tone 00 : : : : 20 X3N X2N X1N X0N Intermediate blue tone 11 Set Display Control Driver duty selection Select driver duty from 1/8 to 1/68. As Y4 Y3 Y2 Y1Y0 is increased from 00001b to 10000b, the number of display lines, N is increased at the same rating. To specify the Y4 Y3 Y2 Y1Y0.
X320 1 0 Y3 0
X220 0 0 Y2 0
X120 1 0 Y1 0
X020 0 0 Y0 0
1 0 * 0
1 0 * 0
0 0 * 0
0 0 Y4 0
Y4 ~ Y0 =
N -1 4
0 1 1 1 1
AA
1 * * * *
0 * * * *
1 * * * *
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0 X4 Y4 Z4 * 1 X3 Y3 Z3 * 0 X2 Y2 Z2 * 1 X1 Y1 Z1 P41 0 X0 Y0 Z0 P40 Set Area Scroll
A dummy byte should be sent before the command byte Y4 to Y0. After the command byte is sent, an additional dummy byte should be sent to the device in order to finish the whole command.
a) Top Block Address X4X3X2X1X0 is used to specify the block address (1 block = 4 lines) at the top of the scrolling area. Top block address = 00000b (POR) b) Bottom Block Address Y4Y3Y2Y1Y0 is used to specify the block address (1 block = 4 lines) at the bottom of the scrolling area. Bottom block address = 00000b (POR) c) Number of specified Blocks The number of specified blocks = Number of (Top fixed area + Scroll area) blocks -1. If bottom scroll or whole screen scroll mode is chosen, the number of specified blocks is set to Z4~Z0 Number of specified blocks = 00000b (POR) d) Area Scroll Mode There are four types of area scroll. P41 P40 Types of Area Scroll 0 0 Center Screen Scroll 0 1 Top Screen Scroll 1 0 Bottom Screen Scroll 1 1 Whole Screen Scroll Type of area scroll = Whole Screen Scroll (POR)
0 1
AB
1 *
0 *
1 *
0 X4
1 X3
0 X2
1 X1
1 X0
Set Scroll Start
X4X3X2X1X0 specify the start block address (1 block = 4 lines) of area scrolling. Start block address = 00000b (POR)
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D/C 0 1
Hex 20
D7 D6 D5 D4 0 0 1 0 * * * *
D3 0 X3
D2 0 X2
D1 0 X1
D0 0 X0
Command Set Power Control Register
Description X0=0: turns off the reference voltage generator (POR) X0=1: turns on the reference voltage generator X1=0: turns off the internal regulator and voltage follower (POR) X1=1: turns on the internal regulator and voltage follower Select booster level
0 1 1
81
1 * *
0 * *
0 X5 *
0 X4 *
0 X3 *
0 X2 Y2
0 X1 Y1
1 X0 Y0
Set Contrast Level & Internal Regulator Resistor Ratio
X3 X2 Boost level 00 3X 01 4X 10 5X 11 6X (POR) a) Select contrast level from 64 contrast steps Contrast increases (V2 decreases) as X5X4X3X2X1X0 is increased from 000000b to 111111b. X5X4X3X2X1X0 = 000000b (POR) b) The internal regulator gain (1+R2/R1) VOUT increases as Y2Y1Y0 is increased from 000b to 111b. The factor, 1+R2/R1, is given by: Y2Y1Y0 = 000: 2.84 (POR) Y2Y1Y0 = 001: 3.71 Y2Y1Y0 = 010: 4.57 Y2Y1Y0 = 011: 5.44 Y2Y1Y0 = 100: 6.30 Y2Y1Y0 = 101: 7.16 Y2Y1Y0 = 110: 8.03 Y2Y1Y0 = 111: 8.89
0
D6 - D7
1
1
0
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1 0 1 1 X0 0 0 1 1 X0 0 X4 Y4 0 0 1 X3 Y3 1 1 0 X2 Y2 0 1 0 X1 Y1 0 1 0 X0 Y0 1 X0 Set Normal/Inverse Display Enter partial Display Exit partial Display Set Display On/Off Enter/Exit sleep mode Enable/disable internal oscillator
X0=0: The contrast set of voltage regulator is Increment / Decrement of the incremented by 1 contrast set X0=1: The contrast set of voltage regulator is decremented by 1 X0=0: normal display (POR) X0=1: inverse display X6X5X4X3X2X1X0: Start COM Address = 000000b (POR) Y6Y5Y4Y3Y2Y1Y0: End COM Address = 000000b (POR) Exit the "partial display mode" by executing the command 10101001b (POR) X0=0: turns off LCD panel (POR) X0=1: turns on LCD panel X0=0: exit the sleep mode. X0=1: enter sleep mode. (POR) X1 X0 01 10 Internal oscillator status ON OFF (POR)
0
A6 - A7
1
0
1
0 1 1 0 0
A8
1 * * 1 1
0 X6 Y6 0 0
1 X5 Y5 1 1
A9 AE - AF
0
94 - 95
1
0
0
1
0
1
0
X0
0
D1 - D3
1
1
0
1
0
0
X1
X0
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D/C 0 1
Hex 82
D7 D6 D5 D4 1 * 0 * 0 * 0 *
D3 0 *
D2 0 *
D1 1 X1
D0 0 X0
Command
Set Temperature compensation coefficient
Description
Average temperature gradients X1 X0 Average Temperature Gradient [%/oC] 00 -0.10 01 -0.15 10 -0.20(POR) 11 -0.25 Command result in No Operation The command should be issued after the execution of the Status Read command Enter the "write display data mode " by executing the command 01011100b. The following byte is used to specify the data byte to be written to the GDDRAM directly. The bit should be stated at logic "1" during the display data is written to the GDDRAM.
0
25
0
0
1
0
0
1
0
1
NOP
0 1
5C
0
1
0
1
1
1 Y21
0 Y11
0 Y01
Y71 Y61 Y51 Y41 Y31
Write display data
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Graphic command table
D/C 0 1 1 1 1 1 1 0 1 92 Hex 83 D7 1 A7 B7 C7 D7 R3 * 1 * D6 0 A6 B6 C6 D6 R2 * 0 * D5 0 A5 B5 C5 D5 R1 * 0 * D4 0 A4 B4 C4 D4 R0 * 1 * D3 0 A3 B3 C3 D3 G3 B3 0 * D2 0 A2 B2 C2 D2 G2 B2 0 * D1 1 A1 B1 C1 D1 G1 B1 1 * D0 1 A0 B0 C0 D0 G0 B0 0 A0
Command
Draw Line
Description Enter the "Draw line mode" by executing the command 10000011. The following four bytes (A0 to A7, B0 to B7, C0 to C7, D0 to D7) are used to specify the start coordinates of X address, start coordinates of Y address, end coordinates or X address and the end coordinates of Y address. The remaining two bytes are used to specify the color.
Remarks: A 97; B 67; C 97; D 67
Fill Enable/Disable Enter the "Fill Enable/Disable mode" by executing the command 10010010. A0=0: Filled color option is disabled (POR) A0=1: Filled color option is enabled
0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1
84
1 A7 B7 C7 D7 R3 * R3 * 1 A7 B7 C7 D7 E7
0 A6 B6 C6 D6 R2 * R2 * 0 A6 B6 C6 D6 E6
0 A5 B5 C5 D5 R1 * R1 * 0 A5 B5 C5 D5 E5 F5 0 A5 B5 C5 D5
0 A4 B4 C4 D4 R0 * R0 * 0 A4 B4 C4 D4 E4 F4 0 A4 B4 C4 D4
0 A3 B3 C3 D3 G3 B3 G3 B3 1 A3 B3 C3 D3 E3 F3 1 A3 B3 C3 D3
1 A2 B2 C2 D2 G2 B2 G2 B2 0 A2 B2 C2 D2 E2 F2 1 A2 B2 C2 D2
0 A1 B1 C1 D1 G1 B1 G1 B1 1 A1 B1 C1 D1 E1 F1 0 A1 B1 C1 D1
0 A0 B0 C0 D0 G0 B0 G0 B0 0 A0 B0 C0 D0 E0 F0 0 A0 B0 C0 D0
Draw rectangle
Enter the "Draw rectangle mode" by executing the command 10000100. The following four bytes (A0 to A7, B0 to B7, C0 to C7, D0 to D7) are used to specify the start coordinates of X address, start coordinates of Y address, end coordinates or X address and the end coordinates of Y address. The next two bytes are used to specify the color. The last two bytes are used to specify the fill color.
Remarks: A C; B D; C 97; D 67
Copy Enter the "Copy mode" by executing the command. The following four bytes (A0 to A7, B0 to B7, C0 to C7, D0 to D7) are used to specify the start coordinates of X address, start coordinates of Y address, end coordinates or X address and the end coordinates of Y address. The remaining two bytes (E0 to E7, F0 to F7) are used to specify the new location of X coordinates and Y coordinates.
8A
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Dim Window
F7 F6 8C 1 A7 B7 C7 D7 0 A6 B6 C6 D6
Remarks: A C; B D; C 97; D 67
Enter the "Dim Window mode" by executing the command 10001100. The following four bytes (A0 to A7, B0 to B7, C0 to C7, D0 to D7) are used to specify the start coordinates of X address, start coordinates of Y address, end coordinates or X address and the end coordinates of Y address. The selected window area will be dimmed by 75% white.
Remarks: A C; B D; C 97; D 67
0 1 1 1 1
8E
1 A7 B7 C7 D7
0 A6 B6 C6 D6
0 A5 B5 C5 D5
0 A4 B4 C4 D4
1 A3 B3 C3 D3
1 A2 B2 C2 D2
1 A1 B1 C1 D1
0 A0 B0 C0 D0
Clear Window
Enter the "Clear Window mode" by executing the command 10001110. The following four bytes (A0 to A7, B0 to B7, C0 to C7, D0 to D7) are used to specify the start coordinates of X address, start coordinates of Y address, end coordinates or X address and the end coordinates of Y address. All pixels contrast will be set to 0.
Remarks: A C; B D; C 97; D 67
Remarks: After executed the graphic command, waiting time is required for update GDDRAM content. (When VDD=1.8~2.6V, waiting time = 250ns/pixel; When VDD=2.6~3.6V, waiting time = 125ns/pixel)
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Extended command table
D/C 0 1 Hex FB D7 D6 1 1 * * D5 1 * D4 1 * D3 1 0 D2 0 B2 D1 1 B1 D0 1 B0 Description Allow user to set bias from 1/ 4 to 1/8 B2B1B0 Bias ratio 000 1/4 bias 001 1/5 bias 010 1/6 bias 011 1/7 bias (POR) 100 1/8 bias 101 Reserved 11X Reserved Set Frame This command uses to change the frame frequency; set frequency and N- the N-line inversion and N-line inversion mode line Inversion F3F2F1F0 1 1 1 1 : 111Hz 1 1 1 0 : 103.5Hz 1 1 0 1 : 98Hz 1 1 0 0 : 93Hz 1 0 1 1 : 89 Hz 1 0 1 0 : 85 Hz 1 0 0 1 : 81.5 Hz 1 0 0 0 : 78 Hz (POR) 0 1 1 1 : 76.5 Hz 0 1 1 0 : 73.5 Hz 0 1 0 1 : 71 Hz 0 1 0 0 : 68 Hz 0 0 1 1 : 66.5 Hz 0 0 1 0 : 64.5 Hz 0 0 0 1 : 62.5 Hz 0 0 0 0 : 60.5 Hz Command Set biasing ratio
0 1 1
F2
1 0 0
1 0 0
1 0 C0
1 0 N4
0 F3 N3
0 F2 N2
1 F1 N1
0 F0 N0
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C0 = 0 : The counter reset per N-line and each frame C0 = 1 : The counter reset per N-line only The second byte data sets the n-line inversion register from 2 to 32 lines to reduce display crosstalk. Register values from 00001b to 11111b are mapped to 2 lines to 32 lines respectively. Value 00000b disables the N-line inversion. 00110 is the POR value. To avoid a fix polarity at some lines, it should be noted that the total number of mux should NOT be a multiple of the lines of inversion (n). 4 bits PWM/FRC or 2 bits PWM + 2 bits FRC selection X1X0 0 0 : 4 bits PWM 0 1 : 4 bits FRC 1 0 : 2 bits PWM + 2 bits FRC (POR) 1 1 : Reserved
0 1 1 1
F7
1 0 0 *
1 0 0 *
1 1 1 *
1 0 0 *
0 1 1 0
1 0 1 1
1 0 X1 0
1 0 X0 1
Select PWM/FRC
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D/C 0 1 1
Hex F6
D7 D6 1 1 0 0 0 0
D5 1 0 0
D4 1 1 0
D3 0 X3 Y0
D2 1 X2 0
D1 1 X1 1
D0 0 X0 0
Command OTP setting
Description This command set the offset value of contrast X3X2X1X0 0 0 0 0 : original contrast (POR) 0 0 0 1 : original contrast + 1 step 0 0 1 0 : original contrast + 2 steps 0 0 1 1 : original contrast + 3 steps 0 1 0 0 : original contrast + 4 steps 0 1 0 1 : original contrast + 5 steps 0 1 1 0 : original contrast + 6 steps 0 1 1 1 : original contrast + 7 steps 1 0 0 0 : original contrast - 8 steps 1 0 0 1 : original contrast - 7 steps 1 0 1 0 : original contrast - 6 steps 1 0 1 1 : original contrast - 5 steps 1 1 0 0 : original contrast - 4 steps 1 1 0 1 : original contrast - 3 steps 1 1 1 0 : original contrast - 2 steps 1 1 1 1 : original contrast - 1 step
0
F8
1
1
1
1
1
0
0
0
OTP programming
Y0 = 0 : Disable the OTP setting you have set Y0 = 1 : Enable the OTP setting you have set (POR) This command start to program LCD driver with OTP offset value. Each bit can be programmed to 1 once. Detail of OTP programming procedure on page 47
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Table 6 - Read Command Table
D/C Hex D7 D6 D5 D4 D3 D2 D1 D0
0 1 1
5D
0
1
0
1
1
1 0 Y21
0 0 Y11
1 0 Y01
0 0 00 0 Y71 Y61 Y51 Y41 Y31
Command Read display data
Description Enter the "read display data mode " by executing the command 01011100b. The next byte is a dummy data. The GDDRAM data will be read form the second byte. The GDDRAM column address pointer will be increased by one automatically after each data read (8levels gray scale mode) OR after each 3-bytes data read. (16-levels gray scale mode).
Remarks: R/W = 1 when D7 to D0 is read
0 0 5D 0 D7 1 D6 0 D5 1 D4 1 D3 1 D2 0 D1 1 D0 Status Register Read D7D6 = 00: Center Screen Scroll Mode D7D6 = 01: Top Screen Scroll Mode D7D6 = 10: Bottom Screen Scroll Mode D7D6 = 11: Whole Screen Scroll Mode D4 = 0: Scan Direction is column direction D4 = 1: Scan Direction is page direction D3 = 0: Display is OFF D3 = 1: Display is ON D2 = 0: Sleep Mode is disabled D2 = 1: Sleep Mode is enabled
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D0 = 0: Partial display is disabled D0 = 1: Partial display is enabled
D1 = 0: Display is Inverse D1 = 1: Display is Normal
Remarks: R/W = 1 when D7 to D0 is read
Note: Command patterns other than that given in Command Table are prohibited. Otherwise, unexpected result will occur. Remarks: "*" denote DON'T CARE bit
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8.1
Data Read / Write
To read data from the GDDRAM, 5Dhex command should be executed then input High to R/W ( WR ) pin and D/ C pin for 6800-series parallel mode. Low to E( RD ) pin and High to D/ C pin for 8080-series parallel mode. No data read is provided for serial mode. In normal mode, GDDRAM column address pointer will be increased by one automatically after each data read in 8-levels gray scale mode OR after each 3-bytes data read in 16-levels gray scale mode. Also, a dummy read is required before the first data is read. See Figure 3 in Functional Description. To write data to the GDDRAM, input Low to R/W ( WR ) pin and High to D/ C pin for 6800-series parallel mode. For serial interface, it will always be in write mode. GDDRAM column address pointer will be increased by one automatically after each data write in 8-levels gray scale mode OR each 3-bytes data write in 16-levels scale mode. The address will be reset to 0 in next data read/write operation is executed when it is 97.
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9
9.1
COMMAND DESCRIPTIONS
Set Column Address (15 Hex)
This command specifies the 8-bit column address of the display data RAM. The start and the end column address are specified by this command. The driver supports up to 98 columns. As the addresses are incremented from the start column to the end column in the column direction scan, the page address is automatically incremented by 1. The column address is then returned to the start column. The column address will be increased by each data access after it is preset by the MCU. Start column < End column must be maintained.
RGB Alignment using 8-levels gray scale mode Column 0 1 P11:0 2 3 P11:1 97 96 95 94 LCD Read Color RGBRGBRGBRGB Direction Data D7 D4 D1 D7 D4 D1 D7 D4 D1 D7 D4 D1 D6 D3 D0 D6 D3 D0 D6 D3 D0 D6 D3 D0 Page D5 D2 D5 D2 D5 D2 D5 D2 BLOCK P10:0 P10:1 0 67 1 66 0 2 65 3 64 4 63 5 62 1 6 61 7 60 : : : : : : : : : : : : : : : : : : : : : : : : : : : 56 11 57 10 14 58 9 59 8 60 7 61 6 15 62 5 63 4 64 3 65 2 16 66 1 67 0
96 1 RGB D7 D4 D1 D6 D3 D0 D5 D2
97 0 RGB D7 D4 D1 D6 D3 D0 D5 D2
COMMON OUTPUTS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 : : : : : : : : : COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67
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: : : : : : : : :
COL288
COL289
COL290
COL291
COL292
SEGMENT OUTPUTS
Table 7 - RAM arrangements of 8-levels gray scale mode
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COL10
COL11
COL0
COL1
COL2
COL3
COL4
COL5
COL6
COL7
COL8
COL9
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RGB Alignment using 16-levels gray scale mode Column P11:0 1 1 0 0 Color R1 G1 B1 R2 G2 B2 R1 G1 B1 R2 G2 B2 Data D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 D7 D3 D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 D6 D2 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D5 D1 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 D4 D0 Page
R1 D7 D6 D5 D4
48 G1 D3 D2 D1 D0
B1 D7 D6 D5 D4
R2 D3 D2 D1 D0
48 G2 D7 D6 D5 D4
B2 D3 D2 D1 D0
} }
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 COL0 COL1 COL2 COL3 COL4 COL5
P11:1 Color Data Page P10:0 0 1 2 3 4 5 6 7 : : : : : : : : : 56 57 58 59 60 61 62 63 64 65 66 67
48 48 47 47 R2 G2 B2 R1 G1 B1 R2 G2 B2 R1 G1 B1 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4
0 0 R2 G2 B2 R1 G1 B1 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
} }
D7 D6 D5 D4 COMMON OUTPUTS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 : : : : : : : : : COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COL288 COL289 COL290 COL291 COL292
LCD Read Direction
BLOCK 0
1
: : : : : : : : : 14
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15
16
P10:1 67 66 65 64 63 62 61 60 : : : : : : : : : 11 10 9 8 7 6 5 4 3 2 1 0
: : : : : : : : :
SEGMENT OUTPUTS
Table 8 - RAM arrangements of 16-levels gray scale mode
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COL10
COL11
COL6
COL7
COL8
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9.2
Set Page Address (75 Hex)
This command enters the page address from 0 to 67 to the RAM page register for read/write operations. The driver supports up to 68 lines. All in all, there are 68 pages. As the addresses are incremented from the start page to the end page in the page direction scan, the column address is incremented by 1. The page address is then returned to the start page. Start page < End page must be maintained.
9.3
Set COM Output Scan Direction (BB Hex)
This command sets the scan direction of the COM output allowing layout flexibility in LCD module assembly. Please refer to the Table 5 on Page 24 for detail mapping. In addition, the display will have immediate effect once this command is issued. That is, if this command is sent during normal display, the graphic display will have vertical flipping effect.
9.4
Set Data Output Scan Direction (BC Hex)
This command sets the DDRAM such that the MPU operates the display data in the internal RAM. A. Normal or Inverse page/column/scan directions The Data Scan direction can be set to either normal or inverse display page and column address scan direction. The column and the page direction are illustrated in the Figure 7 and Figure 8 on page 35 & 36, and Figure 9 on page 36 for example of Normal or Reverse page/column/ scan directions. P12 = 0: Column Direction
P11:0 P11:1 P10:0 0 1 2 : : : 65 66 67 0 97 P10:1 67 66 65 : : : 2 1 0 1 96 2 95 95 2 96 1 97 0
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: : :
P12 = 1: Page Direction
P11:0 P11:1 P10:0 0 1 2 : : : 65 66 67 0 97 P10:1 67 66 65 : : : 2 1 0 1 96 2 95 95 2 96 1 97 0
: : :
Figure 7 - column and page scan direction of 8-level gray scale mode
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P12 = 0: Column Direction
P11:0 P11:1 P10:0 0 1 2 : : : 65 66 67 0 48 P10:1 67 66 65 : : : 2 1 0 0 48 1 47 47 1 48 0 48 0
: : :
P12 = 1: Page Direction
P11:0 P11:1 P10:0 0 1 2 : : : 65 66 67 0 48 P10:1 67 66 65 : : : 2 1 0 0 48 1 47 47 1 48 0 48 0
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Figure 8 - column and page scan direction of 16-level gray scale mode
: : :
P10 = 0 P11 = 0 P12 = 0
P10 = 1 P11 = 0 P12 = 0
P10 = 0 P11 = 1 P12 = 0
P10 = 1 P11 = 1 P12 = 0
P10 = 0 P11 = 0 P12 = 1
P10 = 1 P11 = 0 P12 = 1
P10 = 0 P11 = 1 P12 = 1
P10 = 1 P11 = 1 P12 = 1
Figure 9 - Example of Normal or Reverse page/column/ scan directions
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The parameters following the command set data output scan direction specifies the RGB arrangement and the selection of various gray-scale modes. Please find the information of the RGB arrangement and the gray scale mode in the following section. B. RGB arrangement mode The RGB arrangement mode can be selected according to the following table. Three selection bits will give eight combinations of the RGB arrangements. Each combination set will specify the Red, Green and Blue segment output arrangement in odd and even page.
P22, P21, P20 LINE COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7
... ... ... ... ... ... ... ... ...
COL293
000 001 010 011 100 101 110 111
Even page Odd page 1 2 1 2 1 2 1 2 1 2 1 2 1 2
R R B B R R B B R B B R R B B R
G G G G G G G G G G G G G G G G
B B R R B B R R B R R B B R R B
R R B B B B R R R B B R B R R B
G G G G G G G G G G G G G G G G
B B R R R R B B B R R B R B B R
R R B B R R B B R B B R R B B R
G G G G G G G G G G G G G G G G
B B R R R R B B B R R B R B B R
C. Gray scale mode The gray scale mode can be selected according to the following table. Two types of gray scale mode such that the device can display between 256 colors or 4096 colors.
P32 P31 P30 Numbers of Gary-scale
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Table 9 - RGB Arrangement modes
8 gray-scale mode 16 gray-scale mode
0 0
0 1
1 0
Table 10 - Gray scale selection mode
Black (0, 0, 0) Black (0, 0, 0) Black (0, 0) Red (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) Green (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,1) (1,1,0) (1,1,1) Blue (0,1) (0,1) (0,1) (1,0) (1,0) (1,0) (1,1)
R(D7, D6, D5)
G(D4, D3, D2)
B(D1, D0)
Any one of above
Any one of above
Figure 10 - Examples: 8 gray-scale display arrangement
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Description of different gray-scale display 8-gray-scale display: Table 7 on page 33 shows the arrangement of the display data. The data D7, D6, D5, D4, D3, D2, D1, D0 (RRRGGGBB) is converted into 4-bits data (RRRRGGGGBBBB). The 4-bits data is then stored into the GDDRAM. 16-gray-scale display: Table 8 on page 34 shows the arrangement of the display data. The data D7, D6, D5, D4, D3, D2, D1, D0 is encoded and write into the GDDRAM in three operation cycles. D7, D6, D5, D4, D3, D2, D1, D0: R1, R1, R1, R1, G1, G1, G1, G1 (1 D7, D6, D5, D4, D3, D2, D1, D0: B1, B1, B1, B1, R2, R2, R2, R2 (2
ST
write)
ND
write) write)
D7, D6, D5, D4, D3, D2, D1, D0: G2, G2, G2, G2, B2, B2, B2, B2 (3
RD
9.5
Set Color Look Up Table (CE Hex)
This command transforms the display data (R: 3 bits, G: 3 bits, B: 2 bits) into 4-bit data. The 4 bit data will then be stored into the GDDRAM by choosing colors to represent red, green and blue from 4096 colors. When the GDDRAM output the data, the red, green and blue data are converted back to 8 bit data (R: 3 bits, G: 3 bits, B: 2 bits). The Color Look-up Table must be set when using 8-levels gray scale mode.
9.6
Set Display Control (CA Hex)
This command is used to select the duty ratio of the IC. All available driving duty can be selected using this command. The driving duty can be changed from 1/8 to 1/68.
9.7
Set Area Scroll (AA Hex)
This command specifies the portion of screen for scrolling. The command sets the starting block address, finishing block address, number of specific blocks and the area scroll mode of the area scrolling. Please be noted that the starting block address should be smaller than the finishing block address. The block address increment direction is started at 0 block such that the GDDRAM address corresponds to th the top of the fixed area. Similarly, the block address decrement direction is started at the 16 block such that the GDDRAM address corresponds to the bottom fixed area. The remaining block address excluding the top and the bottom fixed areas are assigned to the scroll plus the background areas. The set area scroll function is divided into four parts. Part I -Specify the top block address of the scroll + the background areas. Specify the 0 block for the top screen scroll or the whole screen scroll. The scroll start block address is also set at this top block address until the scroll start set command is executed. Part II - Specify the bottom address of the scroll + background areas. Specify the 16 block for the bottom or the whole screen scroll. Part III - Specify number of scrolled blocks = number of (Top fixed area + scroll area) blocks -1. When the bottom scroll or whole screen scroll is chosen, the resulted value is identical to the value stated in part II.
th th th
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Part IV Specify the area scroll type. Altogether there are four types of area scroll. Please refer to Table 11 for detail.
P41 P40 Types of Area Scroll
0 0 1 1
0 1 0 1
Center Screen Scroll Top Screen Scroll Bottom Screen Scroll Whole Screen Scroll
Table 11 - Area scrolling selection modes
Center Screen
Top Screen
Bottom Screen
Whole Screen Scroll
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: Fixed Area : Scroll Area Figure 11 - Area scrolling selection modes The area scroll function is executed by prompt in the set area scroll command following by changing the start block address by the set scroll start command. Figure 11 illustrates the operation model of the scrolling function.
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Example: In the Center screen scroll of 1/48 duty (display range: 48 lines = 12 blocks) Description Command Set Area Scroll AAH 8 lines (block 0 & block 1) are specified for the top fixed area - The Top Block Address = Number of the top fixed area =8/4 8 lines (block 15 & block 16) are specified for the bottom fixed area 20 lines (block 10 to block 14) are specified the background areas - The Specified Bottom Block Address = Bottom Block Address + Number of Background area = 9 + (20 / 4) = 14 (0E Hex) 32 lines (block 2 to block 9) are specified the scroll area - Number of Specified Block = Top fixed area + Scroll Area - 1 = (8 / 4) + (32 / 4) - 1 = 9 (09 Hex) Set area scroll mode - Center screen mode Set Scroll start (Scroll range form 02H ~ 0EH) ABH
Data
02H
0EH
09H 00H 02H
DDRAM: LCD panel 0 1 2
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9 10
12 blocks = 48 line
14 15 16 Fixed area Display area Scroll area Background area
Figure 12 - GDDRAM updates for area scrolling
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Block 98 RGB X 68 Line GDDRAM Content Top Fix Area 0 1 2 3 : Scroll Start : : =2 8 9 15 16 Background Area 0 1 Bottom 3 Fix Area 4 : Scroll Start : =3 : 9 10 Example Program of Specified Center Scroll mode. 15 16 Void center_scroll(void) { //Set 1/48 Duty Comm_out (0xCA); 0 Data_out (0x00); 1 Data_out (0x0B); Scroll Start 4 Data_out(0x00); 5 =4 : //Set Area Scroll : Comm_out(0xAA); : Data_out(0x02); // Top Block Address 10 Data_out(0x0E); // Specified Bottom Block Address 11 Data_out(0x09); //Number of Specified Block 15 Data_out(0x00); //Center Screen Mode 16 //Set Scroll Start for (I=0x02; I<=0x0E; I++) { Comm_out(0xAB); //set scroll start Data_out(I); Delay (200); //delay 200ms } }
98 RGB X 48 lines Panel COM0
Scroll Area
COM47 COM0
COM47 COM0
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COM47 COM0 0 1 8 9 : Scroll Start : =8 : 14 2 15 16 COM47
Figure 13 - Example of Specified Center Scroll Mode
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9.8
Set Scroll Start (AB Hex)
This command specifies the starting block address of the area scrolling and then executes the area scroll by changing the start block address dynamically. Start block < End block must be maintained. Please be noted that the set scroll start command should be executed after the set area scroll command.
9.9
Set Power Control Register (20 Hex)
This command turns on/off the various power circuits associated with the chip. There are three power subcircuits (reference voltage generator, internal regulator and voltage follower) could be turned on/off by this command. In addition, the configuration of the internal primary booster (3X/4X/5X/6X) can be selected by this command.
9.10 Set Contrast Level & Internal Regulator Ratio (81 Hex)
This command adjusts the contrast of the LCD panel by changing the LCD driving voltage, VOUT, provided by the On-Chip power circuits. VOUT is set with 64 steps (6-bit) in the contrast control register by a set of compound commands. Please refer to the Figure 14 for the contrast control process flow diagram.
Set Contrast Control Register Contrast Level Data No Changes Complete? Yes
This command also sets the feedback gain of the internal regulator. There are altogether 8 internal regulator gains, which are used for the adjustment of VOUT level. This command is to enable any one of the eight internal resistor (IRS) settings for different regulator gains when using internal regulator resistor network. The Contrast Control Voltage Range curves is referred to the following formula:
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Figure 14 - Contrast Control Flow Set Segment Re-map
R Vout = 1 + 2 *Vcon R 1
63 - Vcon = 1 - * Vref 210
Remarks: TC = -0.20%/ C
o
, where Vref = 1.7V
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Contrast Curve
Vout[V] 18 16 14 12 10 8 6 4 2 0 10 20 30 40 50 60 Contrast[0~63] 70
IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7
Figure 15 - Contrast Control Voltage Range Curve (VDD=2.7V; VCI=3V; Booster level = 6X; TC = -0.20%/ C)
o
Note: The Maximum operation voltage of VOUT is 13.5V with panel load.
9.11 Set Increment/Decrement of the contrast set (D6/D7 Hex)
This command can increase the contrast step by +1 and decrease the contrast set by -1. It is the most convenient way to change the contrast of the display by programming.
9.12 Set Normal/Inverse Display (A6/A7 Hex)
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For a normally white display panel, after the execution of Normal Display command, image data 000(RGB) indicates black pixel and image data FFF (RGB) indicate white pixel. For a normally black display panel, after the execution of Inverse Display command, image data 000(RGB) indicates Black pixel and image data FFF (RGB) indicate white pixel. Example: For a normal White display panel (Set Normal Display: A6 Hex): RAM Content Color R G B F F F White 0 0 0 Black F 0 0 Red 0 F 0 Green 0 0 F Blue For a normal Black display panel (Set Normal Display: A7 Hex): RAM Content Color R G B F F F White 0 0 0 Black F 0 0 Red 0 F 0 Green 0 0 F Blue
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9.13 Enter Partial Display (A8 Hex)
This command and the following parameters specify the display area of the partial display mode. The following figure shows the display and non-display area when the partial display mode is executed.
: Display area
(Partial Display Area) : Non-display area
Figure 16 - Partial display mode
9.14 Exit Partial Display (A9 Hex)
This command exits the partial display mode.
9.15 Set Display On/Off (AE/AF Hex)
This command is used to turn the display on or off. When display off is issued with entire display is on, power save mode will be entered.
9.16 Enter/Exit sleep mode (94/95 Hex)
This command enter/exit the sleep mode.
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9.17 Enable/Disable the internal oscillator (D1/D2 Hex)
This command enables or disables the internal oscillator. The internal oscillator is turned off after hardware or software reset.
9.18 Set Temperature compensation coefficient (82 Hex)
This command sets the average temperature gradients. Four sets of average temperature gradients can be selected. Please refer to the command table for detail description of the average temperature gradients. The 0 default value of the temperature gradient is -0.2 %/ C
9.19 NOP (25 Hex)
A command causing the chip takes No Operation.
9.20 Write display data mode (5C Hex)
This command is used to execute the write display data mode. The display data byte is directly written to the GDDRAM. Please be noted that the D/ C signal should be set to high during the display data is written to the GDDRAM.
9.21 Read display data mode (5D Hex)
This command is used to execute the read display data mode. The display data byte is directly read from the GDDRAM. Please be noted that the D/ C signal should be set to high during the display data is read from to the GDDRAM.
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Graphic Command
9.22 Draw Line (83Hex)
Given the starting point (X1, Y1) and the ending point (X2, Y2), a line will be drawn with the color specified.
The following example illustrates the line drawing procedure. 1. Enter the "draw line mode" by execute the command 83H 2. Set the starting X-coordinates, X1. E.g., 00H. 3. Set the starting Y-coordinates, Y1. E.g., 00H. 4. Set the finishing X-coordinates, X2. E.g., 01H 5. Set the finishing Y-coordinates, Y2. E.g., 01H 6. Set the color to RGB = (0,1,0) e.g., 0FH following by 00H Result: A color line will be drawn between coordinates (0,0) and (1,1) Remarks: X1 97; Y1 67; X2 97; Y2 67
9.23 Fill Enable/Disable (92 Hex)
This command allows the fill color option to be enabled or disabled. This command is applicable to the Draw Rectangle feature. When the selection bit is "0", the fill color option is disabled. When the selection bit is "1", the fill color option is enabled.
9.24 Draw rectangle (84 Hex)
Given the starting point (X1, Y1) and the ending point (X2, Y2), specify the width and height of a rectangle that will be drawn with the color specified. Remarks: If fill color option is disabled, the enclosed area will not be filled.
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The following example illustrates the rectangle drawing procedure. 1. Enter the "draw rectangle mode" by execute the command 8AH 2. Set the starting X-coordinates, X1. E.g., 00H. 3. Set the starting Y-coordinates, Y1. E.g., 00H. 4. Set the finishing X-coordinates, X2. E.g., 02H 5. Set the finishing Y-coordinates, Y2. E.g., 02H 6. Set the color to RGB = (1,0,0) e.g., F0H following by 00H 7. Set the filled color to RGB = (0,1,0) e.g., 0FH following by 00H Result: A filled color square will be drawn with the coordinates of the top left hand corner at (0,0) and the coordinates of the bottom right hand corner at (2,2) Remarks: X1 X2; Y1 Y2; X2 97; Y2 67
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9.25 Copy (8A Hex)
Copy the rectangular region defined by the starting point (X1, Y1) and the ending point (X2, Y2) to location (X3, Y3). There are two possible results with the command copy executed depending on the setting of the start point coordinates and end point coordinates. The following example illustrates the copy procedure.
X1,Y1
X2,Y2
Case 1 - The overlap region will superimpose. 1. Enter the "copy mode" by execute the command 84H 2. Set the starting X-coordinates, X1. E.g., 00H. 3. Set the starting Y-coordinates, Y1. E.g., 00H. 4. Set the finishing X-coordinates, X2. E.g., 02H 5. Set the finishing Y-coordinates, Y2. E.g., 02H 6. Set the New X-coordinates, X3. E.g., 01H 7. Set the New Y-coordinates, Y3. E.g., 01H
X1,Y1
X3,Y3
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X2+X3, Y2+Y3
Case 2 - The original content remains unchanged
X1,Y1
X3,Y3 X2,Y2
X2+X3, Y2+Y3
1. Enter the "copy mode" by execute the command 84H 2. Set the starting X-coordinates, X1. E.g., 00H. 3. Set the starting Y-coordinates, Y1. E.g., 00H. 4. Set the finishing X-coordinates, X2. E.g., 01H 5. Set the finishing Y-coordinates, Y2. E.g., 01H 6. Set the New X-coordinates, X3. E.g., 09H 7. Set the New Y-coordinates, Y3. E.g., 09H Remarks: X1 X2; Y1 Y2; X2 97; Y2 67
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9.26 Dim Window (8C Hex)
This command will dim the window area specify by starting point (X1, Y1) and the ending point (X2, Y2). After the execution of this command, the selected window area will be dimmed by 75% white. Additional execution of this command over the same window area will not change the data content. Remarks: X1 X2; Y1 Y2; X2 97; Y2 67
9.27 Clear Window (8E Hex)
This command sets the window area specify by starting point (X1, Y1) and the ending point (X2, Y2) to clear the window display. The contrast of the window will be set to zero. Remarks: X1 X2; Y1 Y2; X2 97; Y2 67
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Extended Command
9.28 Set biasing ratio (FB Hex)
This command selects a suitable bias ratio (1/4 to 1/8) required for driving the particular LCD panel in use.
9.29 Set Frame Frequency (F2 Hex)
This command specifies the frame frequency so as to minimize the flickering due to the ac main frequency. The frequency is set to 78Hz after POR.
9.30 Set N-line inversion (F2 Hex)
Number of line inversion is set by this command for reducing crosstalk noise. 2 to 32-line inversion operations could be selected. At POR, this operation is set to 0110b (7 lines). It should be noted that the total number of mux should NOT be a multiple of the inversion number (n). Or else, some lines will not change their polarity during frame change.
9.31 Set N-line inversion Mode (F2 Hex)
This command specifies the N-line inversion mode. At POR, The polarity will toggle per N-line and each frame,
otherwise, the polarity toggle per N-line only.
9.32 Select PWM/FRC (F7 Hex)
This command set the Pulse Width Modulation, Frame Rate Control or mix of FWM & FRC.
9.33 OTP setting and programming (F6/F8 Hex)
OTP (One Time Programming) is a method to adjust VOUT. In order to eliminate the variations of LCD module in term of contrast level, OTP can be used to achieve the best contrast of every LCD modules.
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OTP setting and programming should include two major steps. Find the OTP offset and OTP programming as following,
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Step 1. Find OTP offset (1) (2) (3) (4) (5) Hardware Reset (sending an active low reset pulse to RES pin) Send original initialization routines Set and display any test patterns Adjust the contrast value (C:0x81, D:0x00~0x3F, D: 0x00 ~ 0x07) until there is the best visual contrast OTP setting steps = Contrast value of the best visual contrast - Contrast value of original initialization
Example 1: Contrast value of original initialization = 0x20 Contrast value of the best original initialization = 0x24 OTP offset value = 0x24 - 0x20 = +4 OTP setting command should be (C: 0xF6, D: 0x14, D: 0x0A) Example 2: Contrast value of original initialization = 0x20 Contrast value of the best original initialization = 0x1B OTP setting = 0x1B - 0x20 = -5 OTP setting command should be (C:0xF6, D: 0x1B, D: 0x0A) Step 2. OTP programming (6) Hardware Reset (sending an active low reset pulse to RES pin) (7) Enable Oscillator (C: 0xD1) and Exit Sleep Mode (C: 0x94) (8) Connect an external VOUT by closing SW1 (see diagram below) (9) Send OTP setting commands that we find in step 1 (C: 0xF6, D: 0x10~0x1F, D: 0x0A) (10)Send OTP programming command (C: 0xF8) (11)Wait at least 2 seconds (12)Disconnect the external Vout by opening SW1 (13)Discharge the capacitor C by closing the switch SW2 and wait for 1 second (14)Hardware Reset (15)Verify the result by repeating step 1. (2) - (3)
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SSD1788
(8) SW1 R1 C + GND
VOUT
14.5-15.5V R2 SW2 (13)
(1) & (6) & (14)
GND GND
Note:
RES
R1 = 1K ~ 2k ohm R2 = 100 ohm C = 1u ~ 4.7u F
Figure 17 - OTP programming circuitry
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Start Step 2 Step 1
i) Hardware reset ii) Send original initialization routines iii) Set and display any test patterns
i) Hardware reset ii) Enable oscillator
Adjust the contrast level to the best visual level
Connect an external voltage (14.5~15.5V) on VOUT pins
Accept the contrast level on panel?
No
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Yes
OTP setting steps = Adjusted contrast value - Original contrast value
i) Send original initialization routines ii) Set and display any test patterns iii) Inspect the contrast
i) Send OTP setting commands ii) Send OTP programming command iii) Wait > 2 sec vi) Disconnect the external Vout v) Discharge the Vout's capacitor iv) Hardware reset
END
Figure 18 - Flow chart of OTP programming Procedure
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OTP Example program Find the OTP offset:
1. 2. Hardware reset by sending an active low reset pulse to RES pin COMMAND(0XD1); COMMAND(0X94); 3. 4. COMMAND(0X0B); COMMAND(0XCA) DATA(0X10) COMMAND(0XF7) DATA(0X28) DATA(0X2C) DATA(0X05) COMMAND(0XFB) DATA(0X3) 5. COMMAND(0X81) DATA(0X14) DATA(0X05) 6. \\ Set Biasing ratio \\ 1/7 \\ Set target gain and contrast. \\ contrast = 20 \\ IR5 => gain = 7.16 \\Enable oscillator; \\ exit sleep mode; \\ turn on the reference voltage generator, internal regulator and voltage follower; Select booster level. \\ Set Duty ratio \\ 68Mux ([68 / 4] -1 = 16(decimal) / 10(Hex)) \\ Set PWM/FRC \\ pure PWM
\\ Set target display contents COMMAND(0X15) DATA(0x00) DATA(0X61) COMMAND(0X75) DATA(0X00) DATA(0X43) \\ set column address \\ set start column address at 0 \\ set end column address at 97 \\ set page address \\ set start page address at 0
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\\ set end page address at 67 \\ write target content to GDDRAM \\ display on
COMMAND(0X5C) DATA(...) COMMAND(0xAF) 7.
OTP offset calculation... target OTP offset value is +3
OTP programming:
8. 9. 10. 11. 12. Hardware reset by sending an active low reset pulse to RES pin COMMAND(0XAB) COMMAND(0x94) \\ Enable Oscillator \\ Exit Sleep Mode
Connect a external VOUT (14.5V~15.5V) COMMAND(0XF6) DATA(0X13) DATA(0x0A) \\ Set OTP offset value to +3 (0011) \\ 0001 X3X2X1X0 , where X3X2X1X0 is the OTP offset value \\ Enable the OTP setting \\ Send the OTP programming command.
13. 14. 15. 16. 17.
COMMAND(0XF8)
Wait at least 2 seconds for programming wait time. Disconnect an external Vout Discharge the Vout's capacitor Hardware reset by sending an active low reset pulse to RES pin
Verify the result:
18. After OTP programming, procedure 2 to 5 are repeated for inspection of the contrast on the panel.
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Read Status Command
9.34 Status register read
This command will output the status of the device. The following parameters can be monitored by the status read register. 1. Various area scroll mode 2. Column scan direction 3. Page scan direction 4. Display ON/OFF 5. Sleep mode ON/OFF 6. Display Normal/Inverse 7. Partial display mode ON/OFF
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10 MAXIMUM RATINGS
Table 12 - Maximum Ratings (Voltage Referenced to VSS) Symbol Parameter Value Unit
VDD VOUT VCI I TA Tstg Ron
Supply Voltage Input Voltage Current Drain Per Pin Excluding VDD and VSS Operating Temperature Storage Temperature Input Resistance
-0.3 to +4.0 -0.3 to 15 VSS-0.3 to 4.0 25 -40 to +85 -65 to +150 1000
V V V mA C C ohm
o o
Maximum ratings are those values beyond which damages to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that VCI and Vout be constrained to the range VSS < VDD VCI < VOUT. Reliability of operation is enhanced if unused input is connected to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected.
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11 DC CHARACTERISTICS
Table 13 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.6V, TA = -40 to 85C) Symbol Parameter Test Condition Min Typ Max Unit
VDD VDDIO VCI
System power supply pins of the logic block Range System power supply pins of logic block Range Booster Reference Supply Voltage Range
Recommend Operating Voltage Possible Operating Voltage Recommend Operating Voltage Possible Operating Voltage
2.4 1.2 VDD
2.7 -
3.6 VDD 3.6
V V V
IAC
IDP2
ISLEEP
VOUT
VREF
Recommend Operating Voltage Possible Operating Voltage VDD = 2.7V, Voltage Generator On, 5X DC-DC , Write accessing, Tcyc Access Mode Supply Current =5MHz, Typ. Osc. Freq., Display Drain (VDD Pins) On, no panel attached. VDD = 2.775V, VOUT = 10.3V, Voltage Generator On, 5X DC-DC Display Mode Supply Current Converter Enabled, R/W(WR) Halt, Drain (VDD Pins) Typ. Osc. Freq., Display On, no panel attached. VDD = 2.775V, LCD Driving Sleep Mode Supply Current Waveform Off, Oscillator Off, Drain (VDD Pins) R/W(WR) halt. Display On, Voltage Generator Enabled, DC-DC Converter LCD Driving Voltage Generator Enabled, Typ. Osc. Freq., Output (Vout Pin) Regulator Enabled, Divider Enabled. VOUT Converter Efficiency 6X boost, no panel loading o TC0 = -0.10%/ C o TC1 = -0.15%/ C Internal Reference Voltage (T = o TC2 = -0.20%/ C (POR) o 25 C) o TC3 = -0.25%/ C Reference Voltage (T = 25 C) o Reference Voltage (T = -20 C) o Reference Voltage (T = 70 C)
o
-
400
1000
A
-
300
450
A
-
2
5
A
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93 1.64 1.64 1.65 1.65 99 1.69 1.69 1.70 1.70 1.70 1.85 1.55 5 0 TC2 TC2 TC2 Iout=-100A Iout=100A 1.65 1.79 1.50 0.9* VDDIO 0 0.8* VDDIO 0 50 -1 -1 -2
5
-
13.5
V
1.74 1.74 1.75 1.75 1.75 1.91 1.60 VDDIO 0.1*VDDIO VDDIO 0.2*VDDIO -50 1 1 7.5 2
% V V V V V V V V V V V A A A A pF %
VOH1 VOL1 VIH1 VIL1 IOH IOL IOZ IIL/IIH CIN VOUT
Logic High Output Voltage Logic Low Output Voltage Logic High Input voltage
Logic Low Input voltage Logic High Output Current Vout = VDD-0.4V Source Logic Low Output Current Drain Vout = 0.4V Logic Output Tri-state Current Drain Source Logic Input Current Logic Pins Input Capacitance Regulator Enabled, Internal Variation of VOUT Output (VDD is Contrast Control Enabled, Set fixed) Contrast Control Register = 0
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Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
TC0 TC1 TC2 TC3
Average Temperature Gradient Flat Temperature Coefficient Temperature Coefficient 1 Voltage Regulator Enabled Temperature Coefficient 2 (POR) Temperature Coefficient 3
0 -0.12 -0.17 -0.22
-0.10 -0.15 -0.20 -0.25
-0.12 -0.17 -0.22 -0.27
%/ C %/ C %/ C %/ C
o o o
o
The formula for the temperature coefficient is: V at 50 o C - Vref at0 o C 1 TC(%) = ref x x100% 50 o C - 0 o C Vref at 25 o C
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12 AC CHARACTERISTICS
Table 14 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.7V, TA = 25 C) Symbol Parameter Test Condition Min Typ Max Unit
o
Fosc
Oscillation Frequency of Display Timing Generator for: 68 MUX Mode Frame Frequency for: 68 MUX Mode
Internal Oscillator Enabled (default), VDD = 2.7V 465.12 477.36 489.6 kHz
FFRM
b. 98 RGB x 68 Graphic Display Mode, Display ON, Internal Oscillator Disabled, External clock with freq., Fext, feeding to CL pin.
76
78
80
Hz
Remarks:
Fext stands for the frequency value of external clock feeding to the CL pin Fosc stands for the frequency value of internal oscillator
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Table 15 - Parallel 6800-series Interface Timing Characteristics (TA = -40 to 85C, VDD = 2.6V to 3.6V, VDDIO = 1.2V to VDD) Symbol Parameter Min Typ Max Unit
tcycle PW CSL PW CSH tAS tAH tDSW tDHW tACC tOH
Clock Cycle Time (write cycle) Control Pulse Low Width Control Pulse High Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Data Access Time Output Hold time
130 65 65 15 10 10 20 15 20
-
200 60
ns ns ns ns ns ns ns ns ns
Write Cycle
D/C
tAS
R/W
tAH
CS
tF tcycle
PWCSH
tR
PWCSL
E
D0-D7(WRITE)
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tDSW Valid Data
tDHW
The PW CSH timing reference is 50% of the rising / falling edge of E or CS pin. The tDSW and tDHW timing is reference to the 50% of rising / falling edge of E or CS pin.
Read Cycle
D/C
tAS
R/W
tAH
CS
tF tcycle
PWCSH
tR
PWCSL
E
tACC D0-D7(READ) Valid Data
tDHR
tOH
Figure 19 - Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H)
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Table 16 - Parallel 8080-series Interface Timing Characteristics (TA = -40 to 85C, VDD = 2.6V to 3.6V, VDDIO = 1.2V to VDD) Symbol Parameter Min Typ Max Unit
tcycle PW CSL PW CSH tAS tAH tDSW tDHW tACC tOH
Clock Cycle Time (write cycle) Control Pulse Low Width Control Pulse High Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Data Access Time Output Hold time
130 65 65 15 10 10 20 15 20
-
170 60
ns ns ns ns ns ns ns ns ns
Write Cycle
D/C
tAS tAH tR tcycle PWCSH
CS
tF
PWCSL
WR
RD
tDSW
tDHW
D0-D7(WRITE)
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Valid Data
The PW CSL timing reference is 50% of the rising / falling edge of WR or CS pin. The tDSW and tDHW timing is reference to the 50% of rising / falling edge of WR or CS pin.
Read Cycle
D/C
tAS tAH tR
CS
tF
WR
tcycle PWCSH PWCSL
RD
tACC tDHR Valid Data tOH
D0-D7(READ)
The PW CSL timing reference is 50% of the rising / falling edge of RD or CS pin. The tDSW and tDHW timing is reference to the 50% of rising / falling edge of RD or CS pin.
Figure 20 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L)
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Table 17 - Parallel 6800-series Interface Timing Characteristics (TA = -40 to 85C, VDD = 2.4V, VDDIO = 1.2V to VDD) Symbol Parameter Min Typ Max Unit
tcycle PW CSL PW CSH tAS tAH tDSW tDHW tACC tOH
Clock Cycle Time (write cycle) Control Pulse Low Width Control Pulse High Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Data Access Time Output Hold time
250 125 125 15 10 10 20 15 20
-
170 60
ns ns ns ns ns ns ns ns ns
Write Cycle
D/C
tAS
R/W
tAH
CS
tF tcycle
PWCSH
tR
PWCSL
E tDHW D0-D7(WRITE)
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Valid Data
tDSW
The PW CSH timing reference is 50% of the rising / falling edge of E or CS pin. The tDSW and tDHW timing is reference to the 50% of rising / falling edge of E or CS pin.
Read Cycle
D/C
tAS
R/W
tAH
CS
tF tcycle
PWCSH
tR
PWCSL
E
tACC D0-D7(READ) Valid Data
tDHR
tOH
Figure 21 - Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H)
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Table 18 - Parallel 8080-series Interface Timing Characteristics (TA = -40 to 85C, VDD = 2.4V, VDDIO = 1.2V to VDD) Symbol Parameter Min Typ Max Unit
tcycle PW CSL PW CSH tAS tAH tDSW tDHW tACC tOH
Clock Cycle Time (write cycle) Control Pulse Low Width Control Pulse High Width Address Setup Time Address Hold Time Data Setup Time Data Hold Time Data Access Time Output Hold time
250 125 125 15 10 10 20 15 20
-
170 60
ns ns ns ns ns ns ns ns ns
Write Cycle
D/C
tAS tAH tR tcycle PWCSH
CS
tF
PWCSL
WR
RD
tDSW
tDHW
D0-D7(WRITE)
The PW CSL timing reference is 50% of the rising / falling edge of WR or CS pin. The tDSW and tDHW timing is reference to the 50% of rising / falling edge of WR or CS pin.
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tAS tAH tR
Valid Data
Read Cycle
D/C
CS
tF
WR
tcycle PWCSH PWCSL
RD
tACC tDHR Valid Data tOH
D0-D7(READ)
The PW CSL timing reference is 50% of the rising / falling edge of RD or CS pin. The tDSW and tDHW timing is reference to the 50% of rising / falling edge of RD or CS pin.
Figure 22 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L)
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Table 19 - 4-Wires Serial Timing Characteristics (TA = -40 to 85C, VDD = 2.6V to 3.6V, VDDIO = 1.2V to VDD) Symbol Parameter Min Typ Max Unit
tcycle fCLK tAS tAH tCSS tCSH tDSW tOHW tCLKL tCLKH
Clock Cycle Time Serial Clock Cycle Time SPI Clock tolerance = +/- 2 ppm Register select Setup Time Register select Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time
50 90 20 10 30 10 10 15 15
-
20 -
ns MHz ns ns ns ns ns ns ns ns
D/C
tAS tAH tCSH tcycle
CS
tCSS
tCLKL
tCLKH
SCK(D6)
tF tDSW tR
SDA(D7)
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tDHW
Valid Data
CS
SCK(D6)
SDA(D7)
D7
D6
D5
D4
D3
D2
D1
D0
Figure 23 - 4-Wires Serial Timing Characteristics (PS0 = L, PS1 =L)
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Table 20 - 3-Wires Serial Timing Characteristics (TA = -40 to 85C, VDD = 2.6V to 3.6V, VDDIO = 1.2V to VDD) Symbol Parameter Min Typ Max Unit
tcycle fCLK tCSS tCSH tDSW tOHW tCLKL tCLKH
Clock Cycle Time Serial Clock Cycle Time SPI Clock tolerance = +/- 2 ppm Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time
50 10 30 10 10 30 30
-
20 -
ns MHz ns ns ns ns ns ns
CS
tCSS tcycle
tCSH
tCLKL
tCLKH
SCK(D6)
tF tDSW tDHW
SDA(D7)
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Valid Data
CS
SCK(D6)
SDA(D7)
D/C
D7
D6
D5
D4
D3
D2
D1
D0
Figure 24 - 3-Wires Serial Timing Characteristics (PS0 = L, PS1 =H)
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Table 21 - 4-Wires Serial Timing Characteristics (TA = -40 to 85C, VDD = 2.4V, VDDIO = 1.2V to VDD) Symbol Parameter Min Typ Max Unit
tcycle fCLK tAS tAH tCSS tCSH tDSW tOHW tCLKL tCLKH
Clock Cycle Time Serial Clock Cycle Time SPI Clock tolerance = +/- 2 ppm Register select Setup Time Register select Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time
60 90 20 10 30 10 10 15 15
-
16.6 -
ns MHz ns ns ns ns ns ns ns ns
D/C
tAS tAH tCSH tcycle
CS
tCSS
tCLKL
tCLKH
SCK(D6)
tF tDSW tR tDHW
SDA(D7)
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Valid Data
CS
SCK(D6)
SDA(D7)
D7
D6
D5
D4
D3
D2
D1
D0
Figure 25 - 4-Wires Serial Timing Characteristics (PS0 = L, PS1 =L)
SSD1788 Series
Rev 1.2
P 63/71
Jul 2004
Solomon Systech
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Table 22 - 3-Wires Serial Timing Characteristics (TA = -40 to 85C, VDD = 2.4V, VDDIO = 1.2V to VDD) Symbol Parameter Min Typ Max Unit
tcycle fCLK tCSS tCSH tDSW tOHW tCLKL tCLKH
Clock Cycle Time Serial Clock Cycle Time SPI Clock tolerance = +/- 2 ppm Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time
60 10 30 10 10 30 30
-
16.6 -
ns MHz ns ns ns ns ns ns
CS
tCSS tcycle
tCSH
tCLKL
tCLKH
SCK(D6)
tF tDSW tR tDHW
SDA(D7)
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Valid Data
CS
SCK(D6)
SDA(D7)
D/C
D7
D6
D5
D4
D3
D2
D1
D0
Figure 26 - 3- Wires Serial Timing Characteristics (PS0 = L, PS1 =H)
Solomon Systech
Jul 2004
P 64/71
Rev 1.2
SSD1788 Series
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Table 23 - Power Up/Down Timing Characteristics (TA = -40 to 85C, VDD = 2.4V to 3.6V, VDDIO = 1.2V to VDD) Symbol tPR tPD tSTABLE tRES tREADY Parameter Power rise time Power delay time Chip stable time Reset pulse Chip need time after hardware reset Min 10 Typ Max 30 30 10 1 Unit us us us us us
tPR CS VCI
VDD tPD VDDI tSTABLE
RES
tRES
tREADY E
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CS D/C
D0~D7
D1
94
Figure 27 - Power Up
SSD1788 Series
Rev 1.2
P 65/71
Jul 2004
Solomon Systech
www..com www..com 4U
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Symbol tCHARGE tPDOWN
Parameter VOUT Charge up wait time (charge up to 11.7V) Power Hold time
Min 50 50
Typ -
Max -
Unit ms ms
RES
E
CS
D/C
D0~D7
D1
94
20*
0F
81
22
06 tCHARGE
AF
Figure 28 - Initial Code Timing Chart
VCI/VDD/VDDI
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tPHOLD
RES
E
CS tCHARGE D/C
D0~D7
AE
95
D2
D1
* 94
AF
AE
95
D2
Enter power save mode
*
Exit power save mode and return to normal mode
Power off
After enable Booster & Regulator circuitry, there has 200ms mask off period that is used to provide a wait time to charge up VOUT capacitor. Within the mask off period, SEG doesn't have output waveform.
Figure 29 - Power save / power up / power off timing chart
Solomon Systech
Jul 2004
P 66/71
Rev 1.2
SSD1788 Series
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13 APPLICATION EXAMPLES
DISPLAY PANEL SIZE 98RGB X 68
COM34 COM35 : : : : : : : COM66 COM67 SEG97-B SEG97-G SEG97-R SEG96-B SEG96-G SEG96-R : : : : : : : : : : : : : : : : : : : SEG1-B SEG1-G SEG1-R SEG0-B SEG0-G SEG0-R
COM0 COM1 : : : : : : : : COM32 COM33
Output scan command [command: BBH, Data:01H]
ROW67 ..........ROW34 COL0 .....................................................................................................COL293 ROW33 ................ROW0
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SSD1788 IC (DIE FACE UP)
C1 C2
CS RES D / C
SCK SDA VDDIO VDD VCI VSS VOUT
,where VDD & VCI = 2.775V; VDDIO = 2.775V C1 = 1uF ~2.2uF; C2 = 2.2uF ~ 4.7uF. Logic pin connections not specified above: Pins connected to VDD: E; R/W ; D0-D5 Pins connected to VSS: PS0; PS1; RVSS; CVSS; VLREF Pins connected to VCI: VCIX2 Pins connected to VOUT: VHREF
Figure 30 - Application Examples I (4-wires SPI mode)
SSD1788 Series
Rev 1.2
P 67/71
Jul 2004
Solomon Systech
www..com www..com 4U
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DISPLAY PANEL SIZE 98 RGB X 68
COM34 COM35 : : : : : : : COM66 COM67 SEG97-B SEG97-G SEG97-R SEG96-B SEG96-G SEG96-R : : : : : : : : : : : : : : : : : : SEG1-B SEG1-G SEG1-R SEG0-B SEG0-G SEG0-R
COM0 COM1 : : : : : : : : COM32 COM33
Output scan command [command: BBH, Data:01H]
ROW67 ..........ROW34 COL0 .....................................................................................................COL293 ROW33 ................ROW0
SSD1788 IC (DIE FACE UP)
C1 C2
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VCI VSS VOUT VDD
CS RES D / C R / W
,where
E
D0...D7
VDDIO
VDD & VCI = 2.775V; VDDIO = 2.775V. C1 = 1uF ~ 2.2uF. C2 = 2.2uF ~ 4.7uF. Logic pin connections not specified above: Pins connected to VDD: PS0; PS1 Pins connected to VSS: RVSS; CVSS; VLREF Pins connected to VOUT: VHREF Pins connected to VCI: VCIX2
Figure 31 - Application Examples II (6800 PPI mode)
Solomon Systech
Jul 2004
P 68/71
Rev 1.2
SSD1788 Series
www..com www..com 4U
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2.775V
2.775V
2.775V
PS0 PS1 CS RES D/C R/W E D0-D7
VDDIO VDD VCI VCIX2
VOUT VHREF
MCU
SSD1788
VSS CVSS RVSS VLREF
Normal Application
1.8V
2.775V or 1.8V
1.8V
2.775V
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PS0 VDDIO VDD VCI VCIX2 PS1 VOUT
MCU
CS RES D/C R/W E D0-D7
VHREF
SSD1788
VSS CVSS RVSS VLREF
Low Voltage MCU
Figure 32 - Applications notes for VDD/VDDIO connection
SSD1788 Series
Rev 1.2
P 69/71
Jul 2004
Solomon Systech
www..com www..com 4U
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14 PACKAGE INFORMATION
14.1 DIE TRAY DIMENSIONS
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Spec W1 W2 H E K Px Py X Y Z N
mm
(mil)
+0.2 - 0.1 +0.2 - 0.1
76.0 68.0
(2992) (2677) (165) (63) (75) (826) (119) (625) (73) (24)
4.20 0.1 1.60 0.1 1.90 0.1 20.79 0.1 3.03 0.1
15.88 +0.1 -0 1.85 +0.1 -0
0.62 0.05 63
Solomon Systech
Jul 2004
P 70/71
Rev 1.2
SSD1788 Series
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Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part
http://www.solomon-systech.com
SSD1788 Series
Rev 1.2
P 71/71
Jul 2004
Solomon Systech
www..com www..com 4U

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